<?xml version="1.0" encoding="UTF-8"?>
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  <title>DSpace Collection:</title>
  <link rel="alternate" href="http://repository.iiitd.edu.in/xmlui/handle/123456789/212" />
  <subtitle />
  <id>http://repository.iiitd.edu.in/xmlui/handle/123456789/212</id>
  <updated>2026-06-20T10:50:56Z</updated>
  <dc:date>2026-06-20T10:50:56Z</dc:date>
  <entry>
    <title>BluePark : tracking parking and un-parking events in indoor parking lot</title>
    <link rel="alternate" href="http://repository.iiitd.edu.in/xmlui/handle/123456789/335" />
    <author>
      <name>Soubam, Sonia</name>
    </author>
    <author>
      <name>Naik, Vinayak</name>
    </author>
    <author>
      <name>Banerjee, Dipyaman</name>
    </author>
    <author>
      <name>Chakraborty, Dipanjan</name>
    </author>
    <id>http://repository.iiitd.edu.in/xmlui/handle/123456789/335</id>
    <updated>2017-07-24T17:17:49Z</updated>
    <published>2015-10-26T03:37:01Z</published>
    <summary type="text">Title: BluePark : tracking parking and un-parking events in indoor parking lot
Authors: Soubam, Sonia; Naik, Vinayak; Banerjee, Dipyaman; Chakraborty, Dipanjan
Abstract: Finding a parking spot in a busy indoor parking lot is a daunting task. Retracing a parked vehicle can be equally frustrating. We present BluePark, a collaborative sensing mechanism using smartphone sensors to solve these problems&#xD;
in real-time, without any input from user. We propose a novel technique of combining accelerometer and WiFi data to detect and localize parking and un-parking events in indoor parking lot. We validate our approach at the basement parking of a popular shopping mall. The proposed method&#xD;
out-performs Google Activity Recognition API by 20% in detecting drive state in indoor parking lot. Our experiments show 100% precision and recall for parking and un-parking detection events at low accelerometer sampling rate of 15Hz,&#xD;
irrespective of phone’s position. It has a low detection latency of 20 seconds with probability of 0.9 and good location&#xD;
accuracy of 10 meters.</summary>
    <dc:date>2015-10-26T03:37:01Z</dc:date>
  </entry>
  <entry>
    <title>Analyzing mutable checkpointing via invariants</title>
    <link rel="alternate" href="http://repository.iiitd.edu.in/xmlui/handle/123456789/283" />
    <author>
      <name>Aggarwal, Deepanker</name>
    </author>
    <author>
      <name>Kiehn, Astrid</name>
    </author>
    <id>http://repository.iiitd.edu.in/xmlui/handle/123456789/283</id>
    <updated>2017-07-24T17:14:48Z</updated>
    <published>2015-09-10T09:41:32Z</published>
    <summary type="text">Title: Analyzing mutable checkpointing via invariants
Authors: Aggarwal, Deepanker; Kiehn, Astrid
Abstract: The well-known coordinated snapshot algorithm of mutable&#xD;
checkpointing [7{9] is studied. We equip it with a concise formal model&#xD;
and analyze its operational behavior via an invariant characterizing the&#xD;
snapshot computation. By this we obtain a clear understanding of the&#xD;
intermediate behavior and a correctness proof of the fi nal snapshot based&#xD;
on a strong notion of consistency (reachability within the partial order&#xD;
representing the underlying computation). The formal model further enables&#xD;
a comparison with the blocking queue algorithm [13] introduced&#xD;
for the same scenario and with the same objective.&#xD;
From a broader perspective, we advocate the use of formal semantics to&#xD;
formulate and prove correctness of distributed algorithms.</summary>
    <dc:date>2015-09-10T09:41:32Z</dc:date>
  </entry>
  <entry>
    <title>Inference-based LLC-side access pattern estimation for shared cache modeling on commercial processors</title>
    <link rel="alternate" href="http://repository.iiitd.edu.in/xmlui/handle/123456789/271" />
    <author>
      <name>Hemani, Rakhi</name>
    </author>
    <author>
      <name>Banerjee, Subhasis</name>
    </author>
    <author>
      <name>Guha, Apala</name>
    </author>
    <id>http://repository.iiitd.edu.in/xmlui/handle/123456789/271</id>
    <updated>2017-07-24T17:15:40Z</updated>
    <published>2015-05-19T06:50:10Z</published>
    <summary type="text">Title: Inference-based LLC-side access pattern estimation for shared cache modeling on commercial processors
Authors: Hemani, Rakhi; Banerjee, Subhasis; Guha, Apala
Abstract: Cache contention modeling is necessary for good resource utilization&#xD;
on commercial multicore processors. Our goal is to build cache contention&#xD;
models that are sensitive to changes in, 1) the micro-architecture, 2) the&#xD;
co-runner set of each application, and, 3) the inputs to an application.&#xD;
There are two challenges in achieving this goal: 1) it is di cult to deter-&#xD;
mine the LLC behavior for a given memory access pattern, and, 2) it is&#xD;
di cult to obtain the memory access pattern that reaches the LLC.&#xD;
We propose, 1) a methodology to generate the behavioral model of&#xD;
LLCs on protected-technology multicore processors, and, 2) an inference-&#xD;
based approach to estimate the LLC-side memory access patterns. We&#xD;
build a cache contention model that uses the behavioral LLC models and&#xD;
the LLC-side memory access patterns. We evaluated the cache contention&#xD;
model on two commercial multicores with Sandy Bridge and Ivy Bridge&#xD;
micro-architectures respectively, using more than a thousand combina-&#xD;
tions of nine SPEC CPU2006 benchmarks. The average prediction error&#xD;
was 5.74% and 7.27% respectively.</summary>
    <dc:date>2015-05-19T06:50:10Z</dc:date>
  </entry>
  <entry>
    <title>Biclique cryptanalysis of full round AES-128 based hashing modes</title>
    <link rel="alternate" href="http://repository.iiitd.edu.in/xmlui/handle/123456789/224" />
    <author>
      <name>Chang, Donghoon</name>
    </author>
    <author>
      <name>Ghosh, Mohona</name>
    </author>
    <author>
      <name>Sanadhya, Somitra Kumar</name>
    </author>
    <id>http://repository.iiitd.edu.in/xmlui/handle/123456789/224</id>
    <updated>2017-07-24T17:16:23Z</updated>
    <published>2015-03-23T04:05:04Z</published>
    <summary type="text">Title: Biclique cryptanalysis of full round AES-128 based hashing modes
Authors: Chang, Donghoon; Ghosh, Mohona; Sanadhya, Somitra Kumar
Abstract: In this work, we revisit the security analysis of AES-128 instantiated hash modes. We use&#xD;
biclique cryptanalysis technique as our basis for the attack. The traditional biclique approach used&#xD;
for key recovery in AES (and preimage search in AES based compression function) cannot be applied&#xD;
directly to hash function settings due to restrictions imposed on message input due to padding. Under&#xD;
this criteria, we show how to translate biclique technique to hash domain and demonstrate preimage&#xD;
and second preimage attack on all 12 PGV modes. Our preimage attack complexity for all PGV modes&#xD;
stands at 2127.4. The second preimage attack complexities differ based on the PGV construction chosen -&#xD;
the lowest being 2126.3 and the highest being 2126.67 complexity. We also show how to model our attacks&#xD;
under different settings, e.g., when message is padded/ not padded, when chaining variable is known/not&#xD;
known, when full message or key space is available/ not available to the attacker etc. Our attacks require&#xD;
only 2 message blocks with padding included and works on full 10 rounds of AES-128 for all 12 PGV&#xD;
modes. In our attacks, the IV is assumed to be a known constant which is a practical assumption but&#xD;
knowledge of other chaining variables is not required for the attacker. Considering these, our results&#xD;
can be termed as the best so far in literature. Though our attack results do not significantly decrease&#xD;
the attack complexity factor as compared to brute force but they highlight the actual security margin&#xD;
provided by these constructions.</summary>
    <dc:date>2015-03-23T04:05:04Z</dc:date>
  </entry>
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