Year-2019http://repository.iiitd.edu.in/xmlui/handle/123456789/8022024-03-29T11:47:32Z2024-03-29T11:47:32ZCircularly polarized fabry perot cavity antennas with peripheral roughness in superstrate unit cellsJain, SagarRam, Shobha Sundar (Advisor)http://repository.iiitd.edu.in/xmlui/handle/123456789/8302020-09-30T22:00:12Z2019-09-01T00:00:00ZCircularly polarized fabry perot cavity antennas with peripheral roughness in superstrate unit cells
Jain, Sagar; Ram, Shobha Sundar (Advisor)
A Fabry Perot cavity (FPC) antenna consists of a primary radiator at the
base of a dielectric cavity sealed with a partially reflecting surface at the
other end. Excitation from the radiator is partially reflected by the reflecting surface back into the cavity that is backed by a ground plane. Multiple
reflections within the cavity enhances the gain of the antenna. These antennas have been extensively researched and developed for their reduced
fabrication complexity and cost as compared to other high gain planar antennas. Recently, metasurfaces with desirable electromagnetic properties
have been engineered for the partially reflecting surface of FPC antennas
in order to reduce their profile dimensions. These surfaces usually consist
of an array of unit cells that are skillfully designed in order to obtain high
bandwidth or desired polarization. In this thesis, we have examined two unit
cell designs - arc and rectangular loop with the diagonal - with an objective
of achieving circular polarization, broad bandwidth and high gain. Based
on simulations, we achieved minimum axial ratios of 7.46 dB and 7.61 dB
respectively for these two designs. Then we introduced a new design parameter in the form of peripheral roughness in the edges of each of the unit
cells. While the roughness did not significantly improve the axial ratio of the
design with the unit cell arc, we demonstrated a wide return loss bandwidth
of 202.78 MHz (8.86%), an enhanced gain of 9.48 dBi, and a reduced axial
ratio of 4.79 dB for the unit cell with a rectangular loop with diagonal.
2019-09-01T00:00:00ZDevelopment of harmonic radar for insect detectionMumtaz, FatimaRam, Shobha Sundar (Advisor)Purandare, Swapna (Advisor)http://repository.iiitd.edu.in/xmlui/handle/123456789/8192020-06-29T22:00:13Z2019-07-01T00:00:00ZDevelopment of harmonic radar for insect detection
Mumtaz, Fatima; Ram, Shobha Sundar (Advisor); Purandare, Swapna (Advisor)
Harmonic radar technology has been researched and developed for studying the foraging behaviour of insects such as honey bees in order to study their decline in the ecosystem. The traditional radar fails to detect the bees due to their very low radar cross-section caused by their small sizes. The harmonic radar overcomes this limitation by tagging the insects with a harmonic tag consisting of a dipole and a diode. The tag utilizes the nonlinearity property of the diode to convert the carrier frequency of the transmitted signal received by the dipole to its harmonic components, which the dipole re-transmits to the radar. The radar detects the tag on the bee from the second harmonic in the received signal at the radar. This work presents the development of a working prototype of a first generation harmonic radar system to detect the presence of the insect tag at 2.5/5GHz. The thesis discusses the design methodology undertaken to build the radar using offthe-shelf components available in the institute lab. Based on empirical tests on the tag, we estimate the radar probability of detection and probability of false alarms as 88% and 0.3% respectively. The maximum detectable range for a monostatic configuration of the radar is 3.84 m.
2019-07-01T00:00:00ZImpact and detection of partial resistive defects and bias temperature instability on SRAM decoderSingh, ShivendraGrover, Anuj (Advisor)http://repository.iiitd.edu.in/xmlui/handle/123456789/8142020-06-11T22:00:13Z2019-07-01T00:00:00ZImpact and detection of partial resistive defects and bias temperature instability on SRAM decoder
Singh, Shivendra; Grover, Anuj (Advisor)
As technology advances,semiconductor devices are becoming less predictable. This means device failure rate increases as we move down to lower technology nodes. According to ITRS roadmap upto 80% of SOC (Silicon On Chip) area would be occupied by embedded SRAMs (eSRAM) in the next few years. These SRAM units are high density devices and is more susceptible to defects compared to other logic blocks. Along with defects, these SRAM units also suffer from reliability issues like aging impact. There are several computer applications which require extremely high level of reliability of computing system like in Automotive Industry. It is therefore becoming a growing need to detect as well as to find the impact of these defects and reliability issue on SRAM units.
In this work, we analyze the impact of these Partial resistive defects on Static
RandomAccessMemory(SRAM)addressdecoderssidewhichistheleadingcauseofsmall
delays in Wordline activation or deactivation; these are hard to detect and may result in
escapesandreliabilityproblems. HereweinvestigatetheimpactofBTIaswellasresistive
defects at a different location in address decoders. This work also contains the combined effect of both BTI and resistive errors on the decoders. This thesis work also suggests the test mode design for its detection mechanism for these defects. In this test mode, I have shown that the proposed detection mechanism should able to detect the error resistance more than 5K ohm.
2019-07-01T00:00:00ZImproving the retention time of a dopingless 1T DRAM using gate engineeringAgarwal, NimishSaurabh, Sneh (Advisor)http://repository.iiitd.edu.in/xmlui/handle/123456789/8132020-06-11T22:00:09Z2019-07-01T00:00:00ZImproving the retention time of a dopingless 1T DRAM using gate engineering
Agarwal, Nimish; Saurabh, Sneh (Advisor)
In this thesis, a dopingless 1T DRAM with a high retention time is proposed. The high
retention time is achieved by suppressing the diffusion current in the device which is
responsible for degrading the “0” state. In the proposed device, a control gate with an
appropriate workfunction is added in a region adjacent to the source. The control gate
provides the necessary holes that suppress the diffusion current in the “0” state. As a
result, 1/0 read current ratio also increases by 3 orders of magnitude. Furthermore, the
write/hold/readbias conditions of the device and the array topology is designed suchthat the proposed DRAM cell can be integrated compactly. Additionally, it is demonstrated that the DRAM cell operates correctly under various disturb conditions.
2019-07-01T00:00:00Z