http://repository.iiitd.edu.in/xmlui/handle/123456789/140 ECE 2026-05-05T11:19:18Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1925 Radio frequency system-on-chip based platform for over-the-air performance analysis of wireless communication and sensing at millimeter wave Tekchandani, Jeet; Darak, Sumit J. (Advisor) Modern commercial sensing and communication systems that support high mobility primarily operate in the sub-6 GHz frequency band. While robust, this limits achievable data rates to tens of Mbps and leads to latencies exceeding several tens of milliseconds. To overcome these constraints, the mmWave IEEE 802.11ad protocol emerges as a promising candidate, offering significantly higher bandwidth for vehicle-to-vehicle and vehicle-to-infrastructure communication. However, mmWave signals are highly susceptible to atmospheric attenuation, confining their operation to line-of-sight scenarios and necessitating the use of narrow, directional beams. Fast and accurate beam alignment is therefore critical. Recent research has demonstrated that radar sensing can facilitate rapid beam identification while simultaneously supporting environmental perception. Designing a versatile hardware platform to evaluate the over-the-air performance of joint communication and radar sensing is essential. Such a platform enables rigorous assessment of how well existing waveforms perform in realistic environments, particularly in the presence of RF impairments. The first contribution of this thesis is the design and development of a wideband wireless physical layer using Orthogonal Frequency Division Multiplexing (OFDM) on the AMD RF-SoC platform, supporting an instantaneous bandwidth of up to 2.4576 GHz. The proposed architecture follows a hardware–software co-design methodology, wherein baseband signal processing and synchronization algorithms (covering time, frequency, and phase synchronization) are partitioned between the ARM Cortex-A53 processing system and the UltraScale+ FPGA fabric. These components are tightly integrated with the RFSoC’s high-speed on-chip data converters. To enable mmWave transmission, the sub-6 GHz RFSoC output is inter-faced with a multi-antenna mmWave analog front end (AFE) from Sivers Semiconductors, supporting over-the-air communication in the 24.25–29.5 GHz band. Additionally, a custom control interface is developed on the RFSoC to manage AFE parameters such as gain and beam direction dynamically. We demonstrate real-time, end-to-end over-the-air communication and provide a comprehensive bit error rate (BER) analysis under varying modulation schemes, coding rates, bandwidths, and realistic radio channel conditions, including RF impairments and beam misalignments. The second contribution focuses on radar-based sensing using monostatic radar configurations and explores both single-carrier and multi-carrier waveforms commonly employed in radar systems. A key challenge addressed in this work is achieving precise synchronization between the transmitter and receiver, which is critical for accurate target range estimation. Future work will focus on extending the current platform to support Integrated Sensing and Communication (ISAC), a key research priority for 6G networks. By enabling the convergence of communication and radar functionalities on a unified hardware platform, the system will serve as a versatile testbed for evaluating ISAC algorithms in real-world scenarios. Additionally, the platform facilitates over-the-air performance evaluation of artificial intelligence (AI)-enabled physical layer (PHY) techniques, which is an emerging area of interest in both academia and industry. Beyond communication and sensing, the platform also supports advanced channel sounding for in-depth characterization of mmWave channels, taking into account practical impairments such as fading, interference, and RF non-idealities. 2025-05-01T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1896 Impact of approximate adder design choices on sustainability Rao, Thatikonda Gopal; Grover, Anuj (Advisor) Recent advancements in the semiconductor industry have paved the way for a broader use of semiconductor chips in various areas such as computing, data processing, and communication. Adders, which are the smallest and most common building blocks in these applications, play a critical role. With the exponential growth in data, there is a significant increase in power demand, leading to a rising interest in approximate adders. These adders are particularly effective in saving power for error-resilient applications like image and video processing, as well as data computation. As the utilization of semiconductor chips continues to expand, the traditional evaluation framework that focuses on Power, Performance, and Area (PPA) is no longer adequate for assessing the environmental impact of these designs. Consequently, there is a need for a new approach that evaluates designs based on Power, Performance, Area, and Sustainability (PPAS). This sustainability evaluation paradigm broadens the analysis to include the environmental effects of both fabrication and operation, ensuring long-term efficiency and a reduced carbon footprint. In this study, a set of approximate adder architectures has been benchmarked using a novel sustainability-focused evaluation framework in 65-nm low standby power technology. This benchmarking approach allows designers to choose the most efficient and sustainable approximate adder architecture from the available options. 2025-05-14T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1893 Analysis of circuits with partially correlated multi-Vt cell variations using sensitivity modeling and propagation Ubaida, Mohd Abu; Saurabh, Sneh (Advisor) Traditional Static Timing Analysis (STA) tools, commonly used in digital circuit design, usually assume that variations in low-threshold voltage (LVT) and high-threshold voltage (HVT) transistors are fully correlated. This means they treat both types of transistors as if they vary in the same way during the manufacturing process. However, in reality, LVT and HVT transistors are made differently, so their variations are only partly related. This incorrect assumption can lead to errors in estimating the delay and performance of circuits that use both LVT and HVT cells. In this work, we present a new analytical method that accurately calculates the delay variation of logic gates by considering the partial correlation between LVT and HVT transistors. Our method includes a new way to compute the total delay variation of a signal path made up of both LVT and HVT gates. By accounting for the real behavior of process variations, our method improves the accuracy of timing analysis for mixed-Vt circuits. To make this possible, we create a special sensitivity library that helps us measure how changes in transistor properties affect the delay of each cell. This includes not only how LVT cell delays respond to changes in LVT transistors, but also how they respond to changes in HVT transistors and the other way around. This “cross sensitivity” helps us better understand how variations in one type of device affect the other. We test our method on a chain of inverters made from both LVT and HVT gates. The results from our analytical model closely match those from detailed Monte Carlo SPICE simulations, with less than 5% error. Our approach also works well under different input slews, output loads, correlation values between LVT and HVT, and circuit setups. Overall, this framework helps designers more accurately predict timing variations in modern digital circuits and shows how using both LVT and HVT cells can help reduce the negative effects of process variation. It provides useful insights for making more reliable and efficient digital designs. 2025-05-19T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1885 Development of open source multicore system Ayyagari, Krishna; Deb, Sujay (Advisor) This project aims to create an open-source, cache-coherent multicore system that uses the combined processing power of multiple cores arranged in a network-on-chip (NoC) architecture. This semester, the project focused on understanding and implementing the basics of NoC architectures. It started with a detailed study of NoC concepts, including routing techniques and their importance in multicore systems. A simple 2x2 NoC model was developed to test basic functionality and identify challenges related to scaling and performance. In parallel, work was done on the Ibex core, an open-source RISC-V processor developed by the lowRISC community. Functional codes were successfully run on the core, providing insights into its design and capabilities. The study also covered cache coherence, focusing on its role in maintaining data consistency across cores, laying the groundwork for tackling these challenges in future work. 2024-12-01T00:00:00Z