http://repository.iiitd.edu.in/xmlui/handle/123456789/142 2026-04-10T23:12:52Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1836 Impact of Flip-Flop design choices on sustainability for IoT application Khan, Najeeb Mohammad; Grover, Anuj (Advisor) With the rise of semiconductor devices, there has been an exponential increase in their demand. By 2030, approximately 40 billion IoT devices are projected to exist globally. These devices’ design, fabrication, and operation require substantial energy, leading to significant greenhouse gas emissions and a detrimental environmental impact due to climate change. Traditional analyses of Power, Performance, and Area (PPA) are no longer sufficient to address this pressing issue. There is a crucial need for a framework that guides designers in making informed choices during the initial design phase, ensuring that their designs are more sustainable and have a reduced environmental impact. In this study, we present and validate a sustainability framework designed to conduct analyses of embodied, operational, and total carbon footprints, utilizing flip-flop architectures specifically optimized for IoT applications. Our analysis included the implementation of Transmission Gate Flip-Flop (TGFF), Change Sensing Flip-Flop (CSFF), and Contention-Free Change Sensing Flip-Flop (C2SFF) architectures with varied design choice variations. We compared their conventional performance metrics, such as Power, Performance, and Area, while also evaluating their impact on sustainability through the proposed framework. We demonstrated how our framework can aid designers in making informed decisions to achieve the most sustainable designs. The findings reveal that design choices are closely linked to the specific requirements of the target application, significantly influencing the design decisions necessary to attain an optimal level of sustainability. For the proposed formula and assumed factor values, for embodied carbon footprint the area of the design plays a crucial role, whereas for the operational carbon footprint, leakage and dynamic power are pivotal for estimating the sustainability of the design. Additionally, we emphasized the importance of total carbon footprint for sustainability analysis that should be considered alongside PPA to address the growing issue of climate change effectively. 2025-05-14T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1835 Impact of testability on PPAS Horke, Gangaprasad; Grover, Anuj (Advisor) As semiconductor technology advances toward higher integration and functional density, the challenges associated with Design-for-Testability (DFT) have become increasingly significant, particularly in terms of power consumption during testing and chip manufacturing. To analyze the impact of testability on sustainability, this thesis introduces a novel sustainability framework to assess the carbon footprint generated during the testing and manufacturing phases of integrated circuits. The study explores the implementation of DFT using multiple scan insertion techniques, including normal scan chain insertion, DFTmax, and DFTmax Ultra, and com- pares their impact on sustainability. Experimental results demonstrate up to a 10% reduction in test time and a 30% reduction in test data volume owing to shorter scan chain lengths achieved in DFTmax and DFTmax Ultra, while also analyzing their impact on sustainability. The aim of introducing this framework is to provide intelligent guidance, helping de- signers make informed decisions to reduce environmental impact. The metric is expressed in energy units, which can later be converted into CO2 equivalents, providing an estimate of the potential environmental impact. 2025-08-21T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1833 Devolopment of PPAS framework to study the impact of design choices on sustainability in "SAR ADC" architectures Farhan, Ahmad; Grover, Anuj (Advisor) Analog-to-Digital Converters (ADCs) are essential components bridging analog inputs with digital processing systems. Among various architectures, Successive Approximation Register (SAR) ADCs are known for their power and area efficiency but are inherently limited in speed due to their sequential bit-by-bit operation. To overcome this, we implemented and compared two ADC architectures: a conventional SAR ADC and a pipelined SAR ADC, both fabricated in 65nm CMOS technology. The pipelined architecture splits the conversion into two 4-bit stages, allowing it to operate at half the clock frequency while achieving the same throughput as the SAR ADC. Although the SAR ADC occupies about 70% of the area of the pipelined SAR ADC, the pipelined design delivers significantly better performance while maintaining reasonable area and power trade-offs. Additionally, sustainability analysis reveals that the pipelined SAR ADC achieves an approximately 11% lower total carbon footprint compared to the conventional SAR ADC, highlighting the impact of architectural optimization on both performance and environmental metrics. These results underscore that strategic architectural improvements can lead to substantial gains in both system performance and sustainability. 2025-05-10T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1832 Balancing content retention in neural style transfer Agrawal, Yash; Abrol, Vinayak (Advisor) This thesis work focuses on advancements in neural style transfer, a process that enables the blending of content and style features to generate stylized images. It explores feature extraction using two encoders: a VGG19-based encoder and a GLOW based encoder, the latter improving image reconstruction and reducing content leakage through reversible transformations. Various feature fusion techniques are examined, including Adaptive Instance Normalization (AdaIN), Adaptive Attention Normalization (AdaAttN), Self-Attention Network (SANet), Multi-Channel Correlation Network (MCCNet), and Exact Feature Matching, leveraging statistical matching and attention mechanisms. The study also evaluates the impact of different loss functions such as content loss, style loss, identity loss, and contrastive loss on the quality of the output. Custom transformation blocks are introduced, combining methods like feature concatenation, AdaIN with alternative normalizations, and GLOW-based encoders enhanced with attention modules. Existing architectures, such as AdaIN and Exact Feature Matching, are further refined by integrating additional losses to enhance stylization fidelity and preserve content. 2025-05-01T00:00:00Z