http://repository.iiitd.edu.in/xmlui/handle/123456789/1794 Year-2026 2026-06-17T16:43:46Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1984 Towards human-centered data-driven emotion recognition Singh, Pragya; Singh, Pushpendra (Advisor); Kumar, Mohan (Advisor) As artificial intelligence-enabled wearable devices become increasingly integrated into everyday life, they offer new opportunities to continuously monitor physiological signals and support emotional well-being outside clinical settings. Such devices are already capable of monitoring basic health indicators, such as activity levels and heart rate, yet their ability to reliably infer emotional states and support real-world monitoring of mental well-being remains limited. Early research in physiological emotion recognition demonstrates technical feasibility within lab settings, but several challenges must be addressed before these algorithms can be effectively deployed at scale in real life. Key challenges include data availability, data consistency, human-centred validity, and real-world usability. Large, diverse, high-quality labelled emotion datasets remain scarce, limiting robust model development. Existing datasets are often heterogeneous in sensing modalities, devices, experimental protocols, and annotation methods, which complicates benchmarking and hinders model generalisation across contexts. Additionally, emotion labelling inherently involves subjective interpretation, yet many data collection practices insufficiently incorporate participants’ lived experiences, leading to inconsistent annotations and variable data quality. Finally, even technically capable models must align with user needs, expectations, and deployment realities to deliver meaningful support for mental well-being. With everyday mental well-being as the primary application, this dissertation addresses these challenges by (1) systematically analyzing and benchmarking heterogeneous physiological emotion datasets, (2) understanding participant’s perspectives and developing human-centered approaches for collecting more authentic and reliable emotion-labeled data, (3) introducing new datasets and modeling approaches aimed at improving robustness and generalizability, and (4) examining user perspectives to inform the design of deployable mental well-being technologies. Together, these contributions advance the design of physiological emotion datasets, data-collection methodologies, and modelling strategies aimed at improving ecological validity, robustness, and generalisability in emotion recognition research. This dissertation, therefore, offers a comprehensive framework to support the development of data-driven interventions for emotional well-being in everyday settings. Collectively, the work moves the field closer to a future in which wearable intelligent systems can more reliably interpret emotional experiences and deliver meaningful, context-sensitive support for mental well-being in everyday life. 2026-01-01T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1983 Exploring alias analysis based optimizations missed by the compiler Chitre, Khushboo; Kedia, Piyus (Advisor); Rahul, Purandare (advisor) Alias analysis is a technique to determine whether a pair of pointers points to overlapping memory locations. Alias information (especially non-overlapping of pointers) is critical for enabling key transformations such as vectorization, redundant code elimination, loop-invariant code motion, and so on. Context-sensitive interprocedural alias analyses are generally more precise than intraprocedural analyses, but they are often not scalable for large, real-world programs. While context-insensitive interprocedural analyses are more scalable, they significantly sacrifice precision due to call-site merging and conservative assumptions. As a consequence, most of the production compilers sacrifice precision for scalability and implement intraprocedural alias analysis. Moreover, purely static alias analyses are often too conservative when aliasing depends on runtime inputs, calling contexts, or control-flow conditions, especially in cases where pointers overlap only for specific or rare executions. We first proposed a tool to estimate the upper bound on the performance of SPEC benchmarks in the presence of the most precise aliasing information. The key idea was to profile SPEC benchmarks to log alias information, use them to optimize the program, and obtain an upper bound on the likely performance improvement using the most precise alias analysis. Here, the upper bound is an empirical, input-dependent estimate of the performance improvement achievable through improved aliasing precision. We found that an execution time improvement of up to 11.56% is possible for the SPEC benchmarks. Additionally, we found that up to 53.32% execution time improvement is possible for Polybench benchmarks. Polybench benchmarks are used to evaluate the effectiveness of loop transformations. To improve the precision of alias analysis, several prior works propose combining code versioning with dynamic checks to preserve the scalability of alias analyses while selectively improving precision in performance-critical regions. These approaches do not increase alias analysis precision, instead, they use runtime checks to improve the effectiveness of alias analysis in enabling optimizations. These techniques are particularly effective when applied at the loop granularity, since loops often dominate runtime. However, most of these approaches are restricted to loops with either loop-invariant bounds or have very high overheads of dynamic checks, which limit their applicability. This thesis proposes two approaches to reduce the overhead of dynamic checks to constant time. The first approach constrains the allocation size and alignment of the memory objects using a segment-based allocator to reduce the overhead of the dynamic checks to constant time. We achieved a CPU performance improvement of up to 1.47% with a geometric mean of 0.55% for the SPEC benchmarks. The allocator introduced a maximum overhead of 8.36%, with a geometric mean of 1.47% across all SPEC benchmarks. For Polybench benchmarks, we achieved up to 51.11% CPU performance improvement. The allocator introduced a maximum overhead of 5.3%, with a geometric mean of 0.21% across all Polybench benchmarks. Our second approach reduces allocator overhead by selectively constraining memory allocations. We also proposed a region-based allocation strategy that eliminates the need for memory accesses in the dynamic checks. This approach never resulted in performance degradation and achieved improvements of up to 1.88% with a geometric mean of 0.58% on SPEC benchmarks. The maximum CPU overhead of our allocator is 0.57% with a geometric mean of -0.2% for SPEC benchmarks. Both our approaches outperform a previous approach to disambiguate pointers, which reported a 29% overhead for a SPEC CPU 2006 benchmark. The primary contribution of this thesis is the development of a dynamic disambiguation approach that can be applied to enhance the performance of real-world, largescale applications. 2026-04-01T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1966 Towards green and inclusive speech processing: understanding and responsibly mitigating linguistic and accent biases Sharma, V. Divya; Gupta, Anubha (Advisor) High-quality synthetic speech has transformative potential for accessibility, education, entertainment, and personalized human–computer interaction. However, it also poses serious risks: synthetic voices can be exploited for audio deepfakes and impersonation attacks. These risks are magnified in multilingual and low-resource settings, where audio deepfake detection (ADD) and speaker verification (SV) systems exhibit pro-nounced linguistic biases, and the scarcity of large-scale, publicly available datasets limits the development of robust, fair, and inclusive models. Moreover, existing methods for evaluating synthetic speech quality rely primarily on human studies, which are costly, difficult to scale, and often lack reproducibility. Additionally, synthetic speech generation models incur significant carbon emissions, yet environmental sustainability remains largely overlooked. Together, these challenges highlight a critical need for datasets, evaluation frameworks, and bias-mitigation methods that can enable responsible, inclusive, and environmentally conscious speech technologies. To address these gaps, this thesis makes the following key contributions: First, we introduce IndicSynth, a large-scale synthetic speech dataset covering 12 low-resource Indian languages to support multilingual ADD and anti-spoofing research. IndicSynth balances realistic voice mimicry and synthetic diversity. Using IndicSynth, we demon-strate the vulnerability of existing ADD and SV models against synthetic speech attacks. Human evaluation further validates the dataset quality, underscoring the dataset’s utility for security-focused applications. Second, we present Task-Lens, a cross-task profiling framework to mitigate task-resource gaps for underrepresented languages. Using Task-Lens, we profile 34 Indian speech datasets, including IndicSynth, covering 26 languages and eight downstream tasks, based on available metadata. Third, we propose FAtNet and EcoSpeak, which are cost-efficient methods for mitigating linguistic biases in speaker verification, addressing fully and partially cross-lingual scenarios while incorporating Green AI principles by reporting carbon emissions. Finally, we introduce GreenVoice, an automated environment-aware evaluation framework for synthetic speech generation models. GreenVoice cost-effectively highlights high-performing and sustainable generation models for large-scale synthetic speech dataset creation, thus enabling multilingual ADD and anti-spoofing research across more underrepresented languages and accents, beyond IndicSynth. Together, these contributions provide the foundations for building and evaluating speech technologies that are robust, equitable, and inclusive across languages and accents, while promoting environmentally responsible practices and supporting their reliable use in real-world applications. 2026-04-01T00:00:00Z