<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:dc="http://purl.org/dc/elements/1.1/" version="2.0">
<channel>
<title>Year-2023</title>
<link>http://repository.iiitd.edu.in/xmlui/handle/123456789/1045</link>
<description/>
<pubDate>Sat, 11 Apr 2026 15:39:32 GMT</pubDate>
<dc:date>2026-04-11T15:39:32Z</dc:date>
<item>
<title>An investigation on the performance of hybrid visible light and radio frequency for vehicular communication</title>
<link>http://repository.iiitd.edu.in/xmlui/handle/123456789/1378</link>
<description>An investigation on the performance of hybrid visible light and radio frequency for vehicular communication
Singh, Gurinder; Srivastava, Anand (Advisor); Bohara, Vivek Ashok (Advisor)
With the advent of connected autonomous vehicles, we are expecting to witness a new era of un- precedented user experiences, improved road safety, a wide range of compelling transportation applications, etc. A large number of disruptive communication technologies are emerging for the sixth generation (6G) wireless network aiming to support advanced use cases for intelligent transportation systems (ITS). An example of such a disruptive technology is constituted by hybrid Visible Light Communication (VLC) and Radio Frequency (RF) systems, which can play a major role in advanced ITS. The first part of this dissertation highlights the potential benefit of employing vehicular- VLC (V-VLC) along with conventional vehicular-RF (V-RF) for enhanced vehicular message dissemination at road intersection. Further, we propose two practical deployment strategies namely hybrid RF-VLC with relaying and V-RF with Reconfigurable Intelligent Surface (RIS) which may serve as a preferred alternative for future ITS to meet ultra-high reliable and ultra-low latency communication for 6G vehicular networks. In order to provide vehicles with reliable, ubiquitous, and massive connectivity, an appro- priate multiple access (MA) scheme should be adopted. An appealing MA scheme referred to as non-orthogonal multiple access (NOMA) has been gaining significant research attention in vehicular networks among academia and industry. To this end, the proposed framework also aim to present a comprehensive qualitative and quantitative analysis on the performance of Optical Power Domain-NOMA (OPD-NOMA) enabled V-VLC systems. In addition to above, we propose a novel cooperative NOMA (C-NOMA) assisted hybrid visible light and radio frequency communication for improving safety message dissemination at road intersection. Recently, RIS is also emerging as a disruptive communication technology for enhancing the signal quality and transmission coverage in wireless vehicular networks. Despite the widespread interest in applying RISs in various wireless vehicular environments, there is a paucity of intensive research efforts on exploring optical-RIS (O-RIS) for vehicular communication. It is anticipated that 6G-ITS applications viz. autonomous driving, platooning and cooperative driving shall witness the proliferation of such O-RIS and hybrid RF-VLC technologies, while fulfilling stringent 6G key performance indicators (KPIs) requirements. Motivated by the above insights, the proposed work also aim to highlight the advantageous amalgamation of O-RIS and hybrid RF-VLC technologies for enhanced vehicular message dissemination particularly at road intersection. The proposed analytical framework developed in this dissertation allows us to answer several important questions pertaining to transportation networks, smart infrastructure planning, and personnel deployment.
</description>
<pubDate>Fri, 01 Dec 2023 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://repository.iiitd.edu.in/xmlui/handle/123456789/1378</guid>
<dc:date>2023-12-01T00:00:00Z</dc:date>
</item>
<item>
<title>Spatio temporal signal processing harnessing public transit for effective spatiotemporal</title>
<link>http://repository.iiitd.edu.in/xmlui/handle/123456789/1312</link>
<description>Spatio temporal signal processing harnessing public transit for effective spatiotemporal
Charul; Biyani, Pravesh (Advisor)
Public transportation can be a potential source of generating a tremendous amount of data as a part of its daily operation. GPS (Global Positioning System) installed system can be used to track the position of buses and thereby collect a massive stream of traffic speed/ETA (Estimated Time of Arrival) data. An alternate approach called drive-by sensing where sensors can be installed on moving vehicles is a way of collecting highly-granular space/time datasets that can be merged with public transportation (buses) to provide a cost-effective solution. This approach can be used to sense a wide range of phenomena, including traffic speed, air pollution, road lighting, street surface quality, unsafe pedestrian movement, record parking violations, traffic congestion, and crowd flows. Our work mainly focuses on traffic speed and air quality data sensing. The data sampled using sensor sources contain missing values due to sensor malfunctioning or the irregularity in the sensor measurements. The missing data percentage further shoots up in case of drive-by sensing data collection. In this work, we explored three problems spatiotemporal sampling, estimation and prediction for effective and reliable public transportation data acquisition and analysis. First, we propose a Robust Variational Bayesian Subspace Filtering framework for missing data estimation and outlier removal. We also propose an Extreme Matrix completion for missing data estimation using Variational Bayesian Filtering with Subspace information for a higher percentage of missing data. We showed that incorporating the previous subspace information can reduce the sampling complexity of the data; therefore, it can be a potential algorithm to estimate the data in case of moving sensors. Second, we propose Regressive Facility Location, a sampling algorithm to pick sets of paths (using vehicles) that perform representative sampling in space and time. Third, we propose a deep learning-based generative model that predicts the ETA information of buses for a trip and updates it as the trip progresses based on the real-time information.
</description>
<pubDate>Fri, 01 Sep 2023 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://repository.iiitd.edu.in/xmlui/handle/123456789/1312</guid>
<dc:date>2023-09-01T00:00:00Z</dc:date>
</item>
<item>
<title>Generative and adversarial learning for object recognition</title>
<link>http://repository.iiitd.edu.in/xmlui/handle/123456789/1311</link>
<description>Generative and adversarial learning for object recognition
Verma, Astha; Subramanyam, A V (Advisor); Shah, Rajiv Ratn (Advisor)
Generative modeling and adversarial learning have significantly advanced the field of computer vision, particularly in object recognition and synthesis, unsupervised domain adaptation, and adversarial attacks and defenses. These techniques have enabled the creation of more accurate and robust models for critical applications. In particular, we develop algorithms for fine-grained object recognition (Re-ID) and classification tasks. Re-ID involves matching objects across non-overlapping cameras, which is challenging due to visual recognition hurdles like pose change, occlusion, illumination variation, low resolution, and modality differences. On the other hand, object classification is another aim to categorize input data into pre-defined classes, using patterns learned from training data. In this context, our thesis is motivated by the potential of generative modelling to synthesize novel human views, which can be used for unsupervised learning of Re ID models. Unsupervised Re-ID suffers from domain discrepancies between labeled source and unlabeled target domains. Existing methods adapt the model using aug mented samples, either by translating source samples or assigning pseudo labels to the target. However, translation methods may lose identity details, while label assignment may give noisy labels. Our approach is distinct from other methods in that it decou ples the ID and non-ID features in a cyclic manner, which promotes better adaptation to pose and background, thereby resulting in richer novel views. This approach could improve the accuracy of Re-ID models for the unlabeled target domain, thus enhancing their robustness in real-world settings. Furthermore, we aim to analyze the robustness of Re-ID and classification models and propose adversarial attack and defense methods to enhance their reliability. Adver sarial attacks are a malicious technique that manipulates input data to cause machine learning models to make incorrect predictions or classifications. Adversarial defense methods, including adversarial training, certified defense, and detection mechanisms, are used to protect models from such attacks. By integrating adversarial attack and de fense methods into model development and deployment, the risk of incorrect Re-ID and ii misclassification can be minimized, leading to robust models. This is especially impor tant in critical applications such as surveillance and security systems. Our thesis aims to propose adversarial attack and defense mechanisms for Re-ID models and certify the robustness of classification models in both white-box and black-box settings. Specifically, we address the limitations of conventional adversaries that consider Euclidean space and ignore the geometry of the pixels. We propose a stronger at tack by incorporating geometry using the Wasserstein metric attack. To defend against such adversarial attacks, we propose a stochastic neural network that uses isotropic and anisotropic Gaussian noise to parameterize stochasticity. These parameters are learned under a meta-learning framework to make our defense more effective and scalable. Finally, in order to provide a provable guarantee of a black-box model robustness, we propose a certified black-box defense via zeroth-order (ZO) optimization for image classification tasks. Previous works suffer from high model variance and low perfor mance on high-dimensional datasets due to inadequate denoiser design and limited uti lization of ZO techniques. To address these limitations, we introduce a robust UNet denoiser (RDUNet). RDUNet enables the model to learn intricate details while main taining low reconstruction error, surpassing the performance of previously developed custom-trained denoisers. We extensively evaluate our proposed generative and adversarial techniques using publicly available Re-ID and classification datasets - Market-1501, DukeMTMC-ReID, MSMT17, CUHK03, Veri-776, CIFAR-10, CIFAR-100, STL-10, Tiny Imagenet, and MNIST.
</description>
<pubDate>Fri, 01 Sep 2023 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://repository.iiitd.edu.in/xmlui/handle/123456789/1311</guid>
<dc:date>2023-09-01T00:00:00Z</dc:date>
</item>
<item>
<title>Efficient post-silicon debug platforms for future many-core systems</title>
<link>http://repository.iiitd.edu.in/xmlui/handle/123456789/1301</link>
<description>Efficient post-silicon debug platforms for future many-core systems
Rout, Sidhartha Sankar; Deb, Sujay (Advisor)
As the computation is moving towards the exascale era, more and more number of processing cores of heterogeneous natures are getting embedded in a System-on-Chip (SoC). The growing demands for high-performance and increased functionalities would further proliferate this trend in future SoCs. Such many-core systems require efficient and secured interconnection infrastructure for establishing low cost, high speed, and reliable on-chip communication. Thus, the state-of-the-art interconnect modules such as Networks-on-Chip (NoCs) are becoming extremely complex with advanced features like speculation, power management, redundancy, runtime controllability, encryption, etc. The high level of design complexity of the communication network leads to a situation where many functional bugs escape through the pre-silicon verification stage to the actual product on silicon. Even though the processing cores function correctly, bugs in interconnect can very well introduce faults like deadlock, dropped data fault, misroute, etc., which can lead to complete system failure. A substantial percentage of total system errors appear in the interconnect modules of the recent multicore architectures. This necessitates strong post-silicon debug platforms for the NoC subsystems to ensure minimal or no functional communication faults on the actual products. While post-silicon debug provides an efficient platform to remove elusive design bugs, it suffers from very poor system observability and controllability, which is limited to the I/O pins of the chip. To enhance the system’s internal observability during validation, Design for Debug (DFD) structures are instrumented to the original design that includes on-chip trace buffer, trigger unit, trace bus, etc. Traditionally, a trace based postsilicon debug platform is used that stores the runtime traces in the embedded trace buffer and later forwards them to the debug analyzer through a trace port. The drawbacks of such methods are on-chip storage cost because of the trace buffer size and slow trace transfer because of the low bandwidth trace port. In this thesis, we have focused on the development of efficient DFD structures for post-silicon validation of NoC based manycore systems, both in terms of trace reduction and high speed trace communication. Moreover, after the system validation and mass production, the DFD hardware remains vestigial on the system. Reuse of such modules for architectural purposes can compensate for the area overhead introduced by them. Therefore, we have proposed to reuse the DFD infrastructure during the in-field operation mode for the performance enhancement of the NoC based systems. To improve the efficiency of the debug infrastructure, we propose Wireless enabled NoC Debug (WiND) and Redundant Trace Elimination (RTE) frameworks. WiND performs both trace reduction and high speed trace transfer by using the augmented Wireless Interfaces (WIs) in the debug hardware for both test data and trace data communication. RTE majorly focuses on eliminating the redundant traces without degrading the internal observability of the system. To improve the reusability of the debug infrastructure, we propose Re-DeSIGN framework. In this proposal, we reuse trace buffer as extended Virtual Channels (VCs) of NoC routers for network throughput improvement, trace prioritization hardware for critical data prioritization, and trace capture modules for starvation control. This way, ReDeSIGN repurposes almost all the debug units for the performance enhancement of the system during the execution mode. On-chip router buffers consume a significant portion of the total system power. So, to minimize the buffer power in ReDeSIGN framework due to increased number of VCs, we propose DNoC, a dynamic VC power management scheme that activates only the required number of VCs based on the application need during runtime. On-chip wireless infrastructure forms the backbone for WiND and is pivotal for achieving higher debug efficiency. The wireless setup requires a Medium Access Control (MAC) mechanism for an interference free sharing of the wireless channel. The efficiency of a wireless-enabled system is majorly driven by the success of the MAC protocol, as its failure degrades the interconnect performance to a large extent. Towards this end, we propose 2DMAC and Secure MAC to improve the efficiency and security of the wireless communication respectively. 2DMAC can dynamically change the token arbitration pattern and tune the channel hold time of each WI based on its run-time traffic density and data criticality status, resulting in efficient wireless channel utilization. Moreover, 2DMAC prioritizes the critical traffic over the non-critical traffic during the wireless data transfer, leading to application speedup. Wireless channel being a shared medium, a corrupted WI can maliciously hold the channel, resulting in Denial of Service (DoS) or Spoofing in wireless communication. This leads to starvation of healthy WIs and under-utilization of wireless channel. Secure MAC illustrates the threat model and provides countermeasure to establish a secure MAC protocol for the wireless infrastructure embedded to the NoC based many core systems.
</description>
<pubDate>Thu, 01 Jun 2023 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://repository.iiitd.edu.in/xmlui/handle/123456789/1301</guid>
<dc:date>2023-06-01T00:00:00Z</dc:date>
</item>
</channel>
</rss>
