http://repository.iiitd.edu.in/xmlui/handle/123456789/15 Mon, 04 May 2026 18:47:53 GMT 2026-05-04T18:47:53Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1965 Ship marine strategy database access using natural language: an application of LLM-based text-to-SQL model Ghorai, Arunoday; Goyal, Vikram (Advisor) The growing reliance on relational databases across industries and the ability to efficiently query and extract from a structured database has become a crucial skill in the industry. However, the Complexity of SQL Syntax creates a barrier for non-technical uses limiting their ability to interact with databases effectively. Natural Language to SQL (NL-to-SQL) query generation performs a critical task in bridging gap between non-technical users and relational databases and enables intuitive data interaction with out any need for SQL expertise. This thesis first explores various Text-to-SQL approaches, leveraging both proprietary model like Open AI’s GPT-4 and open-source models like RESDSQL, focusing on their performance across benchmark datasets like Spider, CoSQL and SPARC. Additionally, two datasets, MORD and CMEC are prepared from the real world use cases to highlight unique challenges such as hierarchical data structures, string matching operations, and privacy issues. The MORD dataset was queried using GPT-4 integrated with LangChain, to showcase natural language interaction with data and the usability of proprietary models without any tuning to domain specific dataset. Meanwhile the CMEC dataset is a privately curated dataset and access to it needs to be confidential. So we use open source models like RESDSQL that run on local server in order to minimize leakage. The dataset is pre-processed into a relational schema, and RESDSQL is fine tuned on curated NL to SQL pairs to improve performance. String matching techniques are applied to prepare better prompts in order to further enhance the results generated by the model. Sun, 01 Dec 2024 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/1965 2024-12-01T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1928 Automatic speech recognition for code-mixed Indian languages Kumar, Shivam; Akhtar, Md. Shad (Advisor) Code-mixing presents significant challenges for Automatic Speech Recognition (ASR), especially for Indian languages, due to homophone ambiguity, domain-specific word identification, and data scarcity. Traditional ASR models struggle with these complexities, often failing to differentiate between phonetically similar words in multilingual contexts. To address this, we propose CLEAR, a novel rescoring model that integrates descriptive prompting and LLM-based rescoring while analyzing the impact of n-best hypotheses across multiple beam widths. CLEAR enhances ASR performance, achieving S-WER of 26.9, P-WER of 26.46, and T- WER of 25.04—improving by 6.9%, 13.47%, and 4.42%, respectively, over the best baseline, i.e., TDNN. These findings demonstrate that CLEAR effectively resolves homophone ambiguities and refines transcriptions, leading to a 13.56% S-WER reduction over fine-tuned Whisper without extensive pretraining. In addition to improving transcription accuracy, CLEAR introduces a principled framework for handling ambiguous hypotheses in low-resource, script-mixed speech. CLEAR is a generic framework that can be adopted for multiple languages apart from Hindi. This work sets the foundation for more linguistically aware ASR systems tailored for multilingual societies. Thu, 01 May 2025 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/1928 2025-05-01T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1927 Simulating distributed ML training under heterogeneous network infrastructure Temura, Arjun; Shah, Rinku (Advisor) There has been an increasing demand to train ML models, particularly large language models (LLMs), on multiple GPUs to ensure reduced training time and costs. However, making the correct training configuration choice (for example, the number of GPUs, parallelism technique, and network topology) to ensure minimal training time and maximum resource utilisation remains challenging. Distributed ML simulators help users with capacity planning and selecting optimal configuration knobs before training. However, state-of-the-art simulators assume homogeneous compute and network infrastructure. Distributed ML training infrastructure frequently consists of heterogeneous hardware, arising from generational shifts in devices or resource sharing in cloud environments. Several training plans have been introduced in the last few years to make the best out of the available heterogeneous hardware and improve training performance. However, there are no simulation tools that mimic realistic training environments for these heterogeneity-aware training strategies. Generally, heterogeneity-aware training optimisations make guided training plans considering compute or network heterogeneity. Therefore, we design a heterogeneity-aware distributed ML training simulator that supports compute and network heterogeneity. As part of our preliminary analysis, we study GPU communication flows for popular LLMs (GPT, Mixtral) on existing simulation frameworks under realistic training configurations with network heterogeneity. We observe improvement in the completion time of the median flows under heterogeneous configurations during training. Additionally, we develop ideas for effective model partitioning strategies in light of heterogeneous compute. Finally, we briefly discuss the additional abstractions required for our simulator to leverage heterogeneous hardware effectively. Wed, 21 May 2025 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/1927 2025-05-21T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1926 Workload-aware in-network cryptographic primitives for FPGA NIC Peer, Aditya; Shah, Rinku (Advisor) With the increasing demand for low-latency and high-throughput requirements across emerging applications (for example, 5G/6G and the cloud), it has become imperative to offload compute-intensive tasks such as cryptographic processing to specialized accelerators. Given that ASIC-based cryptographic accelerators hinder flexibility, and are unsuitable for dynamic workloads, cloud providers (for example, AWS, Azure, Alibaba, and Google) and telecom operators use FPGA-based accelerators. The state-of-the-art FPGA-based accelerators are designed for high throughput or power efficiency, and they scale by replicating the high-throughput or power-efficient cryptographic cores, which may not be an optimal design for a given workload. We propose the concept of an “Asymmetric Cryptographic Core” to optimize CPU utilization by offloading cryptographic operations. Unlike traditional symmetric cores, our design introduces multiple variants of a specific cryptographic core, each optimized for different performance characteristics such as throughput, power efficiency, and resource usage. These core variants are deployed on an FPGA, dynamically selected based on real-time network workload distribution. This approach enables more efficient use of FPGA resources and delivers improved performance under varying workload conditions. We implemented the Rocca-S algorithm in the FPGA board and designed the variants of the small, medium, and large Rocca-S algorithms. These variants are optimised in terms of throughput, power efficiency, and resource usage. To scale these multiple cryptographic cores and process data streams in parallel, we implemented a load balancer that decides which data packet is supposed to be scheduled to the respective cryptographic core. These choices of asymmetric cryptographic core and scheduling policies will depend upon the deployer’s requirements and varying work-load conditions, to prioritise either throughput, power and resource utilisation of the system. The results showed that the combination of asymmetric cryptographic cores’ performance was comparable with the combination of symmetric cores in terms of throughput, resource and power efficiency, and as the workload distribution varies over time, we observed that the choice of asymmetric and symmetric cores changes in terms of throughput, power efficiency and resource efficiency. Wed, 21 May 2025 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/1926 2025-05-21T00:00:00Z