http://repository.iiitd.edu.in/xmlui/handle/123456789/805 Sat, 11 Apr 2026 15:39:18 GMT 2026-04-11T15:39:18Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1638 Reducing test time using regression algorithms in post silicon validation Mamodia, Shivani; Subramanyam, A V (Advisor) Wed, 01 Jul 2020 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/1638 2020-07-01T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1634 Unsupervised cross modality person Re-Identification Gupta, Sagar; Subramanyam, A V (Advisor) Unsupervised Person Re-Identi cation (Re-ID) su ers severely from the gap in the modality. Many factors pose a challenge to the task, including occlusions, lightning conditions, pose changes, among several others. Various works try to use di erent meth- ods to address the issue while we tried to solve it using GANs. We created images of another domain, conserving the identity of the person while changing the modality. It may so happen that a person moves from a well-lit area to an area where the light is way too low to be detected by the visual sensors. In such a case, the camera switches to IR, and the camera gets images in the Infrared spectrum. The method adopted for the generation of images is cycleGAN combined with pose loss and identity loss which further comprises of style loss and content loss. We are intent on getting IR images of a person with di erent pose whose RGB photos we have while preserving the identity. Besides, we aim to apply the existing state of the art techniques for Unsupervised Person Re-Identi cation for gauging our images. Wed, 01 Jul 2020 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/1634 2020-07-01T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/881 Low power low phase noise LC VCO for sub GHZ range in 40nm technology Sharma, Sapna; Visweswaran, G S (Advisor); Sengupta, Susanta (Advisor) One of the most widely used blocks in Communication System design is Phase locked loop (PLL). PLLs are used as clock generators, frequency synthesizers, clock recovery in microprocessors and many other applications. The key block in design of PLL is the Voltage Controlled Oscillator (VCO). Latest gadgets like smart phones, smart watches, televisions, car electronics are synced to a clock generated by VCO. This thesis focuses on design of LC voltage-controlled oscillators on 40nm technology. With the technology being scaled down, the supply voltage is also scaled down to prevent device breakdown. This results in reduced output swing and degraded phase noise. The quality factor of the LC resonator is low at higher frequency which makes it very difficult to design a low voltage VCO. The main challenges are phase noise, area, performance and variations. This thesis presents the design of low power, low phase noise LC VCO at 800MHz output frequency. The design is implemented on 40nm technology at 1.31V supply voltage achieving a phase noise of -131.7dBc/Hz. The power consumption is 4.3mW. The PVT variations of the design are 4% of nominal value for frequency and 6.8% of nominal value for phase noise. Monte Carlo analysis is also carried out and results are reported. Sat, 01 Aug 2020 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/881 2020-08-01T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/879 High-resolution digital frequency synthesizer for 77 ghz automotive radar transmitters Pandey, Veeraj; Ram, Shobha Sundar (Advisor); Bal, Ankur (Advisor) A high resolution 77GHz linear chirp signal synthesizer for a monostatic frequency modulated continuous wave (FMCW) radar is presented. The proposed linear frequency modulation design uses a fixed frequency multi-stage phase-locked loop (N-PLL) for generating a 77GHz chirp signal. The novel design feature is the incorporation of an additional digital control block clocked from a derived signal output from the N-PLL. A reference oscillator activates the chirp generator block. The clock provided to this block is from the intermediate stage of the N-PLL. Therefore, the generator is clocked at Gigahertz rather than a few Megahertz. This clocking signal can be seen as the sampling frequency of the chirp signal generated. The frequency resolution of the generated chirp signal increases, keeping the bandwidth of chirp intact. The digital block is based on lookup tables. Individual lookup tables and circuits are used when the clock provided by the PLL is of constant frequency, and when the clock provided is "chirpy" due to PLL itself being chirpy. Simulation results using an ideal PLL demonstrate the workability of the proposed method. The all-digital open-loop architecture is simulated with the PLL to generate a high resolution, low noise narrowband chirp with an SFDR performance above 100dB at the PLL output. The digital design does not constrain the fixed frequency PLL design in any way. The resulting chirp signal conformed to above 99.95% linearity. The phase noise modeling of first-order has also been done in the Voltage Controlled Oscillator block of PLL, and relative deviation results of simulation with Gaussian random input have been considered. The approach provides excellent frequency resolution, thereby increasing the unambiguous range of the radar. The high bandwidth of chirp ensures an excellent radar range resolution while the moderate duration of chirp provides a right balance between velocity resolution and maximum unambiguous velocity. Also, the statistics pertaining to these two are improved as a whole. The distortion seen at output manifests only due to PLL non-idealities, of which analysis has been performed, and results have been discussed. The distortion seen at output manifests only due to PLL non-idealities, of which analysis has been completed, and results have been presented. The model can be used alongside applications that require high frequency resolution chirps with large bandwidth Mon, 01 Jun 2020 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/879 2020-06-01T00:00:00Z