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LDO with low quiescent current OTA and capacitance scaling circuit

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dc.contributor.author Bhardwaj, Aman
dc.contributor.author Hashmi, Mohammad S. (Advisor)
dc.date.accessioned 2023-04-05T13:54:15Z
dc.date.available 2023-04-05T13:54:15Z
dc.date.issued 2021-12
dc.identifier.uri http://repository.iiitd.edu.in/xmlui/handle/123456789/1100
dc.description.abstract The efficiency, dependability, and lifespan of any electronic system, particularly battery-powered and portable gadgets, are dependent on a specialized power management unit that offers a clean and controlled power supply. The need for a regulated power supply integrated on a single chip is increasing in various applications ranging from portable devices to biomedical-equipments, which linear regulators accomplish. One such linear regulator is the “Low Dropout Regulator” (LDO), which is utilized to achieve this control even when the power supply or load requirement fluctuates. LDOs are precise and have a quick transient response, making them ideal for controlling on-chip modules. A specific sort of error amplifier is constructed in this study employing an operational transconductance amplifier (OTA) followed by a buffer that switches on and off for specified load situations. The OTA design aims for a low quiescent current with a high gain, which is then utilized to create two proposed LDO circuits for low load and line regulations. A capacitance scaling circuit is designed for the latter suggested architecture of capacitorless LDO to replicate a nano-farad range capacitance from a picofarad-range on-chip capacitor. A 1.2 V bandgap reference with a start-up circuit is also designed for the reference voltage block. We present two LDO circuits in this work. The first is a capacitor-based LDO that uses a 1 μF off-chip capacitor to drive a maximum load current of 300 mA throughout a temperature range of -40o C to 125o C while maintaining a low quiescent current of 590nA – 201.4μA for no-load and max-load circumstances. With a maximum current efficiency of 99.93%, this design achieves load regulation of 0.0158mV/mA and line regulation of 9.47mV/mV. The other proposed design is a capacitorless LDO that uses a capacitance scaling circuit to incorporate a 100pF on-chip capacitor to drive a maximum load of 100mA from -40o C to a temperature range 125o C. The quiescent current varies between 433.9 and 616.6 μA. With a maximum current efficiency of 99.843 percent, this design achieves load regulation of 0.0181mV/mA and line regulation of 46.16mV/mV. en_US
dc.language.iso en_US en_US
dc.publisher IIIT-Delhi en_US
dc.subject Linear regulators en_US
dc.subject Error amplifier en_US
dc.subject Pass transistor en_US
dc.subject Capacitance scaling circuit en_US
dc.subject Voltage reference en_US
dc.title LDO with low quiescent current OTA and capacitance scaling circuit en_US
dc.type Thesis en_US


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