FPGA implementation of RISC-V for efficient edge application

Abstract

Reduced Instruction Set Computing (RISC) is an open-source, exible & easy-to-use ISA widely adopted for many applications. In the previous semester, we built the FPGA based RISCV-32I architecture capable of executing load/store, add/sub/mul operations & other logical operations under complete stalling & bypassing logic. We exploited the capabilities and the limitations of our design by implementing some matrix operations over it. This semester's work focused on prototyping a data-intensive application over the edge on our customised RV32I machine. The idea was to work in the biomedical domain to present a novel solution to worldwide health issues, helping to change how patients are treated and lowering care costs. Hence, we propose an end to end ECG signal based biomedical system to be integrated as our application. While the front end deals with capturing the analog ECG signal, its ampli cation & A-to-D conversion, the back end is majorly focused on an optimised working of ECG processing on the Basys-3 based RV32I machine. In our study, some critical bottlenecks were identi ed, allowing us to tweak the ISA to improve performance necessarily. We developed our own single instruction multiple data (SIMD) instructions other than the existing RISCV instruction set; "Near Memory Computing"(NMC) logic is built to save the memory latency and save the independent instructions from stalling. Our observations from the ECG signal analysis involved detecting R-peaks, computing heart rate, heart rate variability (HRV), the distance between R-peaks, etc. These parame- ters were essential in identifying critical cardiac abnormalities such as "Sinus Arrhythmia" and many more. The exact diagnosis has been captured in our work this semester.