Hardware software co-design of deep learning augmented wireless channel estimation

Abstract

The feasibility study of deep learning (DL) approaches for reliable, flexible, and high throughput wireless physical layer (PHY) has received significant interest from academia and industry. In this direction, 3GPP has set an ambitious goal of introducing standards for intelligent and reconfigurable PHY by 2028. Channel estimation is one of the critical signal processing units of the wireless PHY, and recent works have shown the potential use-case of DL approaches to improve the performance of state-of-the-art statistical channel estimation approaches such as least-square (LS) and linear minimum mean square error (LMMSE). Existing DL-based channel estimation approaches have not yet been realized on system-on-chip (SoC). Our preliminary study shows that their complexity exceeds the complexity of the entire PHY. The high latency of DL is another concern. The work presented in this thesis aims to offer innovative solutions at the algorithm and architecture levels to address these challenges. The first contribution is efficiently mapping LS, LMMSE and DL-based channel estimation approaches on heterogeneous SoC. Via hardware-software co-design and fixed point analysis, we compare the functional correctness, resource utilization, and execution time of existing architectures for a wide range of signal-to-noise ratios (SNR) and wireless channels. Specifically, we highlight the high complexity and latency of existing DL approaches. The second contribution of the thesis is to design a compute-efficient deep neural network (DNN) augmented LS-based channel estimation (LSDNN) algorithm and its efficient mapping on the SoC. We demonstrate substantial savings in complexity and latency without significant degradation in functional accuracy. Specifically, the proposed LSDNN approach offers 88-90% lower latency and 38-85% lower resources than recent DL-based channel estimation approaches. In addition, it offers 75% lower latency and 90-94% lower resource utilization than the LMMSE. The hardware IPs and demonstration on Zynq SoC offer opportunities for commercialization and a framework for verification of upcoming channel estimation algorithms on SoC.