In-network processing for 5G crypto using FPGA-based NICs

Abstract

The latest advancements in the field of 5G telecommunications have proposed the requirements of high speeds (~1 Gbps per user) and low latency (< 1 ms) for a new world of possible applications such as AR/VR, autonomous driving, enhanced mobile broadband, and dense deployments of IoT devices. To achieve such high-performance requirements for the 5G network components and applications, solutions such as kernel bypass techniques and offload to programmable data plane hardware have been proposed. The management plane of the 5G network implements security algorithms to ensure confidentiality and integrity within the wireless network, between the wireless and the mobile core (wired), and between the components within the mobile core network. The 5G network implements the New Generation Encryption Algorithms (NEA) and New Generation Integrity Algorithms (NIA) to support ciphering and integrity, respectively. Some research has proposed to offload the 5G components, such as the Access and Mobility Function (AMF), New Generation Node B (gNB), and User Plane Function (UPF), to the programmable data planes (PDPs) to accelerate the performance and reduce power consumption. With the offloading of security-related network functions like AMF and gNB, it becomes crucial to offload the cryptographic algorithms implemented by these functions to avoid hypervisor/kernel stack traversal, ensure better throughput, and lower network latencies. Our project aims to design an in-network 5G security solution that promises high speed, low processing latency, scalability, dynamic reconfigurability, and reduces power consumption by leveraging FPGA-based network hardware.