IIIT-Delhi Institutional Repository

Browsing Electronics and Communication Engineering by Title

Browsing Electronics and Communication Engineering by Title

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  • Openlane RTL-to-GDSII (R2G2) flow for home-grown soc 
    Malhotra, Ishan; Grover, Sarthak; Deb, Sujay (Advisor) (IIIT-Delhi, 2023-11-29)
    Applying the OpenROAD toolchain to a Cortex-M0-based System on Chip (SoC) is the first step in this ground-breaking project's RTL-to-GDSII (R2G2) pipeline. The OpenROAD toolchain and scripts must be carefully modified and ...
  • Optimizing medical costs and resource utilization using causal inference and explaining the model’s predictions 
    Jain, Tanisha; Prasad, Ranjitha (Advisor) (IIIT-Delhi, 2023-07)
    Machine learning (ML) models that accurately predict treatment effects and related healthcare costs can bring significant efficiencies in the healthcare industry. These models could help reduce fatalities resulting from ...
  • Performance analysis of future wireless communication systems under residual hardware impairments 
    Shaikh, Mohd Hamza Naim; Bohara, Vivek Ashok (Advisor); Srivastava, Anand (Advisor) (IIIT-Delhi, 2023-01)
    The widespread proliferation of wireless services in daily life has boosted the demand for very high data rates. This plunge in data rate leads to an increase in energy consumption. As a result, in order to meet the ...
  • Performance improvement in LiFi using advanced modulation techniques and learning-based coexistence with WiFi 
    Ahmad, Rizwana; Srivastava, Anand (Advisor) (IIIT-Delhi, 2021-05)
    Keywords- LiFi, WiFi, O-OFDM, PAPR, DP-OFDM, GMSK, DFT, O-GFDM, HLWN, load balancing, RL, RWP, ORWP. A significant increase in wireless communication has been observed over the past decade. The existing radio frequency ...
  • Performing crypto algorithms at 100 gbps bandwidth 
    Kumar, Prateek; Shah, Rinku (Advisor); Darak, Sumit Jagdish (Advisor) (IIIT-Delhi, 2023-12-05)
    Data centers increasingly offload compute-intensive tasks to SmartNICs to optimize server resources for diverse applications. These SmartNICs, equipped with FPGA boards, are programmed to process data, substituting server ...
  • Personal health record app 
    Shariq, Mohammad; Sethi, Tavpritesh (Advisor) (IIIT-Delhi, 2023-11-29)
    The government of India launched the National Digital Health Mission(NDHM) initiative to make healthcare more accessible by digitizing patient data and unifying processes. We propose implementing an NDHM-compliant personal ...
  • Personalized unsupervised federated autoencoders 
    Arora, Kanika; Prasad, Ranjitha (Advisor) (IIIT-Delhi, 2023-07)
    An immense amount of data is generated daily usingmodern technologies in autonomous vehicles, IoT, smart grids, etc. But unfortunately, this data generated at the edge cannot be used for any machine learning model training ...
  • Post disaster wireless communication 
    Kumar, Rajesh; Sujit, PB (Advisor) (IIITD-Delhi, 2019-11-26)
    We had seen many natural and human-made disasters like Tsunami In Chennai in December 2015 and cyclone storm ‘Hudhud’ in 2014 in North Indian Ocean. Which caused substantial damage to cellular network infrastructure and ...
  • Power estimation of in-memory compute based memory arrays using simulink blocks 
    Mohd, Aamir; Grover, Anuj (Advisor) (IIIT-Delhi, 2022-10)
    System-on-Chip (SoC) incorporates all the components of any system onto a single integrated circuit. Their compact, power-efficient architecture allows them to be used in various applications like automotive, consumer ...
  • Power estimation using transaction level modeling 
    Chandoke, Nidhi; Deb, Sujay (Advisor) (2015-12-07)
    The increasing complexity of current day Systems-on-Chip and the rising market demands for low power devices has necessitated the need to perform power analysis of the complete system-on-chip at system level. This ...
  • Power network analysis using frequency domain approach 
    Jain, Abhishek; Hashmi, Mohammad S. (Advisor) (2015-12-07)
    With reduction in size and shrinking in geometry, we have reached a point in time in which we no more can draw a direct correlation of the performance of the IC design with respect to the number of transistors on a single ...
  • Power- and performance-aware on-chip interconnection architectures for many-core systems 
    Mondal, Hemanta Kumar; Deb, Sujay (Advisor) (IIIT-Delhi, 2017-04)
    Networks-on-Chip (NoCs) are fast becoming the de-facto communication infrastructures in Chip Multi-Processors (CMPs) for large-scale applications. The traditional approaches of implementing a NoC with planar metal interconnects ...
  • A practical methodology to waive marginal timing violations using machine learning 
    Kumar, Rajat; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2022-07)
    Achieving timing closure is a challenging task, and it becomes more complicated due to the artificial pessimism in the traditional timing models of the flip-flops. During the signoff stages, we can alleviate this problem ...
  • Predictive analysis of safety subsystems in memories for diagnostic coverage 
    Srinivasan, Arvind; Hashmi, Mohammad S. (Advisor); Janardan, Dhori Kedar (Advisor) (2015-12-07)
    Automobile safety is becoming an important subject because of the large number of electronic systems being integrated within a System on Chip (SoC) and with the use of current state-of-the-art technology, safety is becoming ...
  • Probability of target detection in bistatic and multistatic radars 
    Singhal, Shubhi; Ram, Shobha Sundar (Advisor) (IIIT-Delhi, 2022-05)
    In the first part of the work, we evaluate the detection performance of a bistatic radar using a metric called bistatic radar detection coverage probability. The setting considered for the target detection consists of noise ...
  • Process, voltage and temperature compensated oscillator for phase change memories 
    Tyagi, Vivek; Hashmi, Mohammad S. (Advisor) (2017)
    Non Volatile Memories (NVM’s) are an integral part of every System-on-Chip (SoC) for retaining the data when power goes off. Phase change memory (PCM) is type of NVM and exhibits significant advantages over existing NVM ...
  • Radar sensor networks 
    Badri, M.; Raman, Rajiv (Advisor); Ram, Shobha Sundar (Advisor) (IIIT- Delhi, 2021-05)
    This work aims at interference mitigation in recently booming automotive radar networks, via careful beam forming techniques based on Geometric Algorithms and Optimizations. We first thoroughly explore a relatively simple ...
  • Razor flop based on chip delay measurement 
    Vasisth, Aditya; Hashmi, Mohammad S. (Advisor); Jain, Abhishek (Advisor) (2015-12-05)
    Moving towards deep submicron technologies, consideration for design margin will increase. In these technologies, process variation will increase the requirements of design margins. Lower supply voltage and higher clock ...
  • Realistic rendering of 3D avatar using physics simulation and minimal sensors 
    Acharya B, Srikrishna; Sujit, PB (Advisor) (2014-07-10)
    Physics simulation o ers the option of truly receptive and realistic animation. Although wide ac- ceptance of physics simulation for the animation, commercial applications still relies on kinematics- based approaches for ...
  • Realizing and functionality using single tunnel field-effect transistor 
    Banerjee, Saptak; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2018-07)
    In this thesis, a single Double-Gate Tunnel Field-Effect Transistor (DGTFET) is proposed to realize the AND functionality. Using two-dimensional device simulations, it is shown that a single DGTFET can realize logic ...

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