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Results 1-10 of 31 (Search time: 0.01 seconds).
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Issue Date
Title
Author(s)
2017-06
High efficiency fully integrated PLL based low-dropout voltage regulator
Singh, Ankush
;
Hashmi, Mohammad S. (Advisor)
2015-12-07T08:58:28Z
Identification of weak bits in SRAM
Kumar, Gundu Anil
;
Hashmi, Mohammad S. (Advisor)
2015-12-07T06:28:21Z
Predictive analysis of safety subsystems in memories for diagnostic coverage
Srinivasan, Arvind
;
Hashmi, Mohammad S. (Advisor)
;
Janardan, Dhori Kedar (Advisor)
2016-09-12T10:09:54Z
Mitigation of cold boot attack using an encrypted memory controller
Walia, Preet Kaur
;
Hashmi, Mohammad S. (Advisor)
2017-07-09
Time to digital converter for all digital PLL in 65 nm CMOS technology
Shukla, Vipra
;
Hashmi, Mohammad S. (Advisor)
2017
Process, voltage and temperature compensated oscillator for phase change memories
Tyagi, Vivek
;
Hashmi, Mohammad S. (Advisor)
2016-09-12T09:45:38Z
Exploration of test methodologies to detect weak bits in SRAMs
Batra, Nidhi
;
Hashmi, Mohammad S. (Advisor)
2017-03
Design of GaN HEMT broadband power amplifiers
Banerjee, Deepayan
;
Hashmi, Mohammad S. (Advisor)
2015-12-05T06:56:34Z
Razor flop based on chip delay measurement
Vasisth, Aditya
;
Hashmi, Mohammad S. (Advisor)
;
Jain, Abhishek (Advisor)
2017
High resolution low power discrete-time sigma-delta ADC with input offset compensation technique
Kalla, Shivam
;
Hashmi, Mohammad S. (Advisor)
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Ahlawat, Anuradha
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Arora, Disha
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Bansal, Shrestha
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Batra, Nidhi
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Batra, Shipra
1
Bhardwaj, Aman
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DALAL, NEHA
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Garg, Sakshi
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Gupta, Rahul
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CMOS
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SRAM
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Non-volatile memory
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40nm CMOS
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Amplifier design
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Bandgap
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Capacitance scaling circuit
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Cellular Communication
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Cold boot attack
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