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Issue Date	Title	Author(s)
2022-07	A practical methodology to waive marginal timing violations using machine learning	Kumar, Rajat; Saurabh, Sneh (Advisor)
2018-07	Realizing and functionality using single tunnel field-effect transistor	Banerjee, Saptak; Saurabh, Sneh (Advisor)
2019-07	Improving the retention time of a dopingless 1T DRAM using gate engineering	Agarwal, Nimish; Saurabh, Sneh (Advisor)
2025-05-19	Analysis of circuits with partially correlated multi-Vt cell variations using sensitivity modeling and propagation	Ubaida, Mohd Abu; Saurabh, Sneh (Advisor)
2019-07	Investigation of timing of logic gates realized using probabilistic spin logic (PSL)	Bhatia, Ishan; Saurabh, Sneh (Advisor)
2022-08	An artificial neural network based incremental placer for wire length reduction	Gagandeep; Saurabh, Sneh (Advisor)
2024-06-01	Accounting for the correlation between low-threshold and high-threshold transistors using analytical techniques	Pandey, Prashasti; Saurabh, Sneh (Advisor)