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UVM based STBUS veri cation IP for verifying SoC

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dc.contributor.author Samanta, Pranay
dc.contributor.author Deb, Sujay (Advisor)
dc.date.accessioned 2014-07-10T09:49:33Z
dc.date.available 2014-07-10T09:49:33Z
dc.date.issued 2014-07-10T09:49:33Z
dc.identifier.uri https://repository.iiitd.edu.in/jspui/handle/123456789/148
dc.description.abstract The ever increasing advances in the integrated circuit technology made it possible for electronic system designers to assemble complete systems-on-chips (SoC). As these SoCs have been used in computer, graphics, and networking hardware systems, the complexity of functionality within them have rapidly increased. At the same time shrinking time to market leaves little room for errors in the design. Hence functional veri cation has become one of the major tasks in committing chips to fabrication. Just as designs are pushing towards reusable environment so must the veri cation environment. As veri cation itself takes 70% of the design time, the need of standalone, pre-veri ed veri ca- tion infrastructure is arisen so that veri cation does not become the bottleneck for the designers. The Veri cation Intellectual Property (Veri cation IP/VIP) which can be easily plugged in the simulation-based tests, is an important component of such infrastructure. In this dissertation the modeling of VIP of STBUS protocol has been presented, and in the process STBUS protocol has been also veri ed. The use of STBUS VIP has been shown by modeling a veri cation environment for verifying a SoC. The coverage analysis has been done to check how much jump-start the veri cation IP can produce in achieving the coverage goal quickly. en_US
dc.language.iso en_US en_US
dc.subject UVM en_US
dc.subject STBUS en_US
dc.title UVM based STBUS veri cation IP for verifying SoC en_US
dc.type Thesis en_US


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