Abstract:
With the scaling of semiconductor technology nodes, the impact of process-induced variations has increased. Statistical static timing analysis accounts for global and local variations in the timing analysis. The present methodology considers all the devices to have correlated variations at the global level. However, because of the difference in the fabrication steps of multi-threshold voltage transistors, their variations are not entirely correlated. Ignoring the varying correlations can lead to inaccuracies in the timing analysis. In this work, we have proposed an analytical method to compute variance in the currents and CMOS inverter delays as a function of device parameter variations and their correlations. Furthermore, we have compared the standard deviations obtained using the proposed analytical model and the experimental standard deviations obtained using Monte Carlo simulations. The results show that the error in the standard deviation of saturation currents obtained using the analytical model with respect to the experimental data is less than 1% and that in the inverter delay is less than 5%. Additionally, the results obtained using the proposed model with varying correlations between low and high-threshold transistors show the same trend as those obtained using Monte Carlo simulations. Hence, the proposed modeling technique could be employed in the future for timing analysis that statistically accounts for global variations among miscorrelated transistors.
