Abstract:
As semiconductor technology advances toward higher integration and functional density, the challenges associated with Design-for-Testability (DFT) have become increasingly significant, particularly in terms of power consumption during testing and chip manufacturing. To analyze the impact of testability on sustainability, this thesis introduces a novel sustainability framework to assess the carbon footprint generated during the testing and manufacturing phases of integrated circuits. The study explores the implementation of DFT using multiple scan insertion techniques, including normal scan chain insertion, DFTmax, and DFTmax Ultra, and com- pares their impact on sustainability. Experimental results demonstrate up to a 10% reduction in test time and a 30% reduction in test data volume owing to shorter scan chain lengths achieved in DFTmax and DFTmax Ultra, while also analyzing their impact on sustainability. The aim of introducing this framework is to provide intelligent guidance, helping de- signers make informed decisions to reduce environmental impact. The metric is expressed in energy units, which can later be converted into CO2 equivalents, providing an estimate of the potential environmental impact.
