Low power standard cell library design in 180nm

Abstract

This thesis investigates the design and optimization of a low-power subtractor circuit tailored for inclusion in a standard cell library fabricated using the SCL 180nm CMOS process. The project explores multiple logic design methodologies—Gate Diffusion Input (GDI), Transmission Gate (TG), and AOI/OAI logic—with the objective of identifying an optimal architecture that minimizes power and area while preserving functional accuracy and signal integrity. Simulations were conducted using Cadence Virtuoso and ADE L environments, providing insight into design trade-offs and performance constraints at the transistor level. The study culminates in a robust AOI/OAI-based implementation, validated against a predefined 30T standard cell subtractor, and is aimed at achieving an energy-efficient arithmetic unit for digital IC design.