Abstract:
This semester’s thesis work presents an automated framework for generating and verifying Sys- temVerilog Assertions (SVAs) using Large Language Models (LLMs), with the goal of minimizing manual effort in formal hardware verification. Leveraging Google’s Gemini LLM and Cadence JasperGold, the system translates English property descriptions into syntactically and seman- tically valid assertions, verifies them, and iteratively refines incorrect outputs based on formal feedback. The framework explores three distinct models: a Normal Model for one-shot asser- tion generation, a Feedback Model that incorporates verification feedback for correction, and a Thumb Rule Model that applies heuristics derived from expert-crafted assertion templates. Experimental results across 90 property prompts and 14 RTL designs demonstrate that the Thumb Rule Model provides the highest first-attempt success rate, while the Feedback Model offers robust recovery from errors in non-standard scenarios. This hybridized approach com- bines domain-specific heuristics with the generative power of LLMs to significantly improve automation and accuracy in formal verification workflows.
