Power, Performance, Area and Sustainability (PPAS)

Abstract

The escalating complexity of modern integrated circuits necessitates rigorous optimization of power, performance, and area (PPA) metrics within advanced CMOS technologies. Concomi- tantly, the semiconductor industry faces increasing pressure to mitigate environmental impact through sustainable design practices. This paper presents a comprehensive investigation into PPA optimization and sustainability assessment of fundamental VLSI building blocks, with particular focus on adder and amplifier topologies through an RTL to GDS flow. Our methodology is implemented using a complete RTL to GDS digital design flow within the Cadence tool suite: RTL design and functional verification, logic synthesis, placement and rout- ing, and GDS generation, supplemented by schematic capture and custom layout in Cadence Virtuoso. Post-layout parasitic extraction and device-level modeling feeding into Cadence Eldo simulations enable accurate evaluation of trade-offs among static and dynamic power consump- tion, propagation delay, and silicon area across PVT corners. Additionally, we introduce sus- tainability metrics such as the energy-delay product and estimated carbon footprint to quantify the environmental ramifications of each implementation. Building upon these results, we extend our framework to explore various multiplier architectures of array multiplier within the same RTL to GDS environment. The proposed approach aims to identify multiplier designs that satisfy stringent PPA constraints while minimizing energy consumption, thereby advancing the development of eco-conscious VLSI circuits. Our findings underscore the efficacy of a holistic, CMOS-centric RTL to GDS design strategy in achieving high-efficiency, low-impact hardware solutions. The methodologies and insights presented herein provide a blueprint for future research in sustainable VLSI design.