Analysis of circuits with partially correlated multi-Vt cell variations using sensitivity modeling and propagation

Abstract

Traditional Static Timing Analysis (STA) tools, commonly used in digital circuit design, usually assume that variations in low-threshold voltage (LVT) and high-threshold voltage (HVT) transistors are fully correlated. This means they treat both types of transistors as if they vary in the same way during the manufacturing process. However, in reality, LVT and HVT transistors are made differently, so their variations are only partly related. This incorrect assumption can lead to errors in estimating the delay and performance of circuits that use both LVT and HVT cells. In this work, we present a new analytical method that accurately calculates the delay variation of logic gates by considering the partial correlation between LVT and HVT transistors. Our method includes a new way to compute the total delay variation of a signal path made up of both LVT and HVT gates. By accounting for the real behavior of process variations, our method improves the accuracy of timing analysis for mixed-Vt circuits. To make this possible, we create a special sensitivity library that helps us measure how changes in transistor properties affect the delay of each cell. This includes not only how LVT cell delays respond to changes in LVT transistors, but also how they respond to changes in HVT transistors and the other way around. This “cross sensitivity” helps us better understand how variations in one type of device affect the other. We test our method on a chain of inverters made from both LVT and HVT gates. The results from our analytical model closely match those from detailed Monte Carlo SPICE simulations, with less than 5% error. Our approach also works well under different input slews, output loads, correlation values between LVT and HVT, and circuit setups. Overall, this framework helps designers more accurately predict timing variations in modern digital circuits and shows how using both LVT and HVT cells can help reduce the negative effects of process variation. It provides useful insights for making more reliable and efficient digital designs.