Inference-based LLC-side access pattern estimation for shared cache modeling on commercial processors

Abstract

Cache contention modeling is necessary for good resource utilization on commercial multicore processors. Our goal is to build cache contention models that are sensitive to changes in, 1) the micro-architecture, 2) the co-runner set of each application, and, 3) the inputs to an application. There are two challenges in achieving this goal: 1) it is di cult to deter- mine the LLC behavior for a given memory access pattern, and, 2) it is di cult to obtain the memory access pattern that reaches the LLC. We propose, 1) a methodology to generate the behavioral model of LLCs on protected-technology multicore processors, and, 2) an inference- based approach to estimate the LLC-side memory access patterns. We build a cache contention model that uses the behavioral LLC models and the LLC-side memory access patterns. We evaluated the cache contention model on two commercial multicores with Sandy Bridge and Ivy Bridge micro-architectures respectively, using more than a thousand combina- tions of nine SPEC CPU2006 benchmarks. The average prediction error was 5.74% and 7.27% respectively.