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LLVM backend development for ReISC architecture

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dc.contributor.author Gupta, Pooja
dc.contributor.author Guha, Apala (Advisor)
dc.date.accessioned 2015-12-02T12:43:02Z
dc.date.available 2015-12-02T12:43:02Z
dc.date.issued 2015-12-02T12:43:02Z
dc.identifier.uri https://repository.iiitd.edu.in/jspui/handle/123456789/345
dc.description.abstract In today's complex environment, it is very crucial for the devices to feature low power consumption at allow cost. Internet of things is predicted to bring an era where everything will have chips embedded in them, be it a household appliance, mobile device or industrial equipment. To fulfill this vision, todays power-needy devices need to be replaced by less power consuming devices. Ultra Low Power chip design has this property which increases its demand. ReISC (Reduced energy Instruction Set Computer) is an embedded architecture meant for low power devices with high performance applications. It provides support for secure data, parallel operations and fast interrupt response. To leverage these features of this architecture, building a compiler is essential. This work describes the design and implementation of a new backend for the ReISC architecture based on Low Level Virtual Machine (LLVM) compiler infrastructure. This thesis contains the detailed discussion of translation of the code in LLVM intermediate representation to ReISC assembly code. It also includes the comparison between assembly code generated by the LLVM back-end and code generated by the ReISC toolchain. The analysis of results implies that the LLVM backend generated code is in close proximity to toolchain generated code. en_US
dc.language.iso en en_US
dc.title LLVM backend development for ReISC architecture en_US
dc.type Thesis en_US

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