Methodological framework for automation of hardware software co-validation of an IP

Abstract

The VLSI industry is witnessing rapid changes driven by the growing mar- ket requirements. In order to maintain their competitive quotient, reducing the time to market of their IC products has become a prime concern of the semiconductor companies. The reason is the direct impact of the time to market on the pro t margins of a company. The product development cycle includes formation of the product speci cations, design implementation and design veri cation. The process of verifying a new product design consumes a signi cant time portion of its development cycle. The verifying process starts after the product speci cations are formed, continuing through the various later phases. One of the phases is after the rst silicon prototype of the product is fabricated, and is known as the post silicon validation (PSV). Although considered as a bottleneck in the product development cycle, it is an absolute requirement being the nal step towards mass manufactur- ing of the product. While standardized automation tools exists for other phases like veri cation, the PSV phase has remained void of such tools due to the varying properties of IC products. Traditional PSV methods have failed to keep pace with the VLSI advancements. Creative strategies are required by the semiconductor industry to reduce the product cycle time and address the new requirements of the PSV process. This work presents one such approach which allows introduction of automation in PSV to re- duce the time to market of the IC products along with other requirements which are at-speed testing, hardware and software co-validation and reduc- tion in the resource investment in PSV. Using this approach, the average validation time of a PSV for NAND and an SPI NOR ash controller IPs are reduced by 76% and 61% respectively compared to the times required, if the automation framework is not utilized.