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Razor flop based on chip delay measurement

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dc.contributor.author Vasisth, Aditya
dc.contributor.author Hashmi, Mohammad S. (Advisor)
dc.contributor.author Jain, Abhishek (Advisor)
dc.date.accessioned 2015-12-05T06:56:34Z
dc.date.available 2015-12-05T06:56:34Z
dc.date.issued 2015-12-05T06:56:34Z
dc.identifier.uri https://repository.iiitd.edu.in/jspui/handle/123456789/364
dc.description.abstract Moving towards deep submicron technologies, consideration for design margin will increase. In these technologies, process variation will increase the requirements of design margins. Lower supply voltage and higher clock frequency will further alleviate the issue of design margin. As technology progresses, STA (static timing analysis) is becoming a very important issue. With the increase in frequencies, there is a clear trend towards increasing setup and hold time violations. Thus, there is an increasing requirement of accurate and quick measurement techniques, to take care of all such requirements. Over reliance on tools for STA analysis can lead to inflexible designs. Off chip measurement techniques, such as spectrum analyzer, sampling oscilloscope and time interval analyzer measure delay but as the complexity of the system and chip integration increases, these off chip instruments become unviable. This dissertation discusses available techniques for on chip delay measurement. Several metrics, such as resolution, area and linearity have been compared. Furthermore, discussions on setup time violations are provided. Violation in setup time occurrence has been ingeniously used to predict the access time for data in NVM. (Non Volatile Memory). en_US
dc.language.iso en en_US
dc.title Razor flop based on chip delay measurement en_US
dc.type Thesis en_US

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