dc.description.abstract |
The increasing complexity of current day Systems-on-Chip and the rising
market demands for low power devices has necessitated the need to perform
power analysis of the complete system-on-chip at system level. This would
facilitate selection of optimal system architecture and opportunity to optimize
the selected system design for reduced power consumption in the silicon as
much more design optimization opportunities are available at system level
in contrast to Register Transfer Level (RTL).
Transaction level model provides the conceptual implementation of the
design at higher abstraction level above RTL and is available much early in
the design cycle as against RTL, hence, is being used in industries for early
software development and functional verication of the hardware.
In this work, we present a methodology to estimate power consumption of
an IP at transaction level by capitalizing the existing transaction level model
of the corresponding IP. The proposed methodology makes use of SystemC
transaction level model not speci cally designed with power estimation in
mind.
We then validate the proposed method against RTL for accuracy and speed.
The proposed approach enables estimation of dynamic power consumption
and leakage power consumption with an error within 20% of RTL and total
power consumption with an error within 12% with respect to RTL. In
terms of speed-up, the proposed approach enables 10x faster simulation,
hence, faster power estimation compared to estimating power at RTL. The
accuracy and speed-up of the proposed approach are illustrated through
experimental results. |
en_US |