Exploration of real value modelling for complex mixed signal verification

Abstract

With the demand to have more functionality in today's systems, the high performance SOC will have to further accommodate Analog and Mixed Signal (AMS) designs. Also, due to increasing unpredictability and complexity of such system, circuit SPICE and Fast SPICE simulation can not deliver a verification arrangement on time. This leads to growing necessity of methodology for accurate and fast verification of AMS designs. In this dissertation, we have presented a novel approach for AMS verification which uses well known Real Value Modelling (RVM) concepts. RVM processes oating-point real numbers like analog world, based on discrete events. The developed veri cation technique in this work makes it possible to behaviourally model analog e ects such as supply ramp behavior, PVT variations, using event driven simulators and compatible with existing digital verification techniques. This significantly reduces the verification time for Full Chip Simulations (FCS). Also, the advantages of this approach are illustrated by taking Phase locked loop as an examples.