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Development and enhancement of verification environment for complex designs

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dc.contributor.author Madan, Raghav
dc.contributor.author Deb, Sujay (Advisor)
dc.date.accessioned 2015-12-07T07:52:37Z
dc.date.available 2015-12-07T07:52:37Z
dc.date.issued 2015-12-07T07:52:37Z
dc.identifier.uri https://repository.iiitd.edu.in/jspui/handle/123456789/372
dc.description.abstract Digital VLSI design verification is a process of checking and verifying the correctness of design functionality with respect to the documented specications. Functional verification of a complex IP or sub-system, formed by integrating the IPs, accounts for more than half of the time and efforts required for product development. Development of testbench environment for complex designs requires a strategic planning and lot of human efforts. Therefore, in order to dwindle human involvement and efforts, a predefined verification methodology can be followed which provides a structure for generic implementation and development of testbench environment by adopting a standard hardware verification language. Universal Verification Methodology is a recent one that provides a structured implementation of testbench for simulation based verification and also enables reusability of verification components by virtue of System Verilog language. A preponderance of testbench development is devoted to self-checking mechanism. Therefore, verification environment development time and engineeros efforts can further be abated with the availability of well-defined and exhaustive self-checking mechanism. In this dissertation, the development of UVM based verification environment for complex designs along with implementation and performance analysis of different kind of self-checking mechanisms has been presented. This will assist the verification engineers to quickly develop the verification environment with selection of best possible self-checking mechanism as per the design type and complexity. This will also reduce their efforts for checking the functionality of design, checking bus protocol communication with DUV, searching for hidden bugs in the design with the aim of reaching higher coverage goals by taking memory and timing requirement into consideration. en_US
dc.language.iso en en_US
dc.title Development and enhancement of verification environment for complex designs en_US
dc.type Thesis en_US


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