Identification of weak bits in SRAM

Abstract

Up to 70% of Systems on a Chip (SoC) area are occupied by embedded memories. In order to achieve higher robustness, embedded SRAMs (eSRAM) are often used in SOC applications. However, due to advancement in technology it is nearly impossible to guarantee the first silicon success in an IC. Furthermore in high density devices like SRAMs, device variations are very common because of continuous scaling down of length, width and threshold voltage of the transistor devices. In these variations, if the variations occurring in the devices are random then it becomes a very tedious job to achieve silicon success. For example, random variations like number and location of dopant atoms in the channel will cause asymmetric variations and degrades the performance of the devices. It is therefore becoming a growing need to validate the silicon to detect and fix bugs in an IC after the design process. Thereby, it is largely viewed as an art with very few systematic solutions. As a result, post-silicon validation is becoming an emerging research topic for major innovations in electronic design automation. In this work, we conducted a comprehensive analysis for detecting the memory cells which exhibits weak Static Noise Margin (SNM), write time, write margin and identified the factors causing these cells to exhibit weak properties. In this work the term ‘weak’ is qualified as the cells exhibiting weak SNM, cell current, write margin and write time. Based on these characteristics, two methods are proposed for identifying the weak bits. For verification of these methodologies in SRAM, a single port high density STM critical path was considered in 28nm technology.