An effective and efficient methodology for SoC power management through UPF

Abstract

With technology scaling and increase of chip complexity, power consumption of chip has been rising and its power architecture is getting complicated. Many power management techniques like power gating, multi-voltage, multi-threshold are applied to reduce power dissipation of devices. UPF is an IEEE 1801 standard format to describe the power architecture, also called as power intent, including power network connectivity and power reduction methods. It enables verification of power intent at early phases of the design cycle. The UPF developed should be consistent with the design at all stages of the design cycle and it should be updated according to the modifications made in the design. In conventional UPF flow through design cycle, few practical challenges are faced. Many bugs are not detected at earlier phases which might lead to the wrong implementation of power intent. In addition, parallel development of power intent for complex designs, limitations of UPF standard to describe few power intent components effectively and time-consuming conventional UPF flow hinder efficient UPF development and management. In this work, a UPF methodology is proposed which detects bugs at earlier stages and enables development of ideal UPF at RTL stage itself, which is to be just refined successively at later stages. This methodology also ensures proper restructuring and demotion of UPF along with automation of UPF development, demotion and verification. The proposed methodology is applied on the development of power-aware set-top box device, as a case study, with power gating and multi-supply voltage techniques applied. The results show that an overall error reduction of 81% is noticed with 63% at RTL stage. Verification time is reduced by 93% due to automation and early detection of issues. Automation of UPF development and demotion saved time by around 99% and 97% respectively.