Power- and performance-aware on-chip interconnection architectures for many-core systems

Abstract

Networks-on-Chip (NoCs) are fast becoming the de-facto communication infrastructures in Chip Multi-Processors (CMPs) for large-scale applications. The traditional approaches of implementing a NoC with planar metal interconnects have high latency and significant power consumption overhead. This is mainly due to the multi-hop data exchange using wired links, specifically when the number of cores is significantly high. To address these problems, Wireless NoCs (WNoCs) that augment multi-hop wired interconnects in a NoC with high-bandwidth, single-hop, long-range wireless links are being explored. Although multi-hop communication is replaced by WNoC, still, NoC components including wireless transceivers consume a significant portion of chip power, which is one of the major bottlenecks in NoC architectures for CMPs. With progressing generations and system sizes, this proportion increases exponentially. Another important concern with the existing WNoCs is the performance limitations due to single frequency channel communication with omnidirectional antenna setups. These bottlenecks open up new opportunities for detailed investigations into the power and performance efficiency of WNoCs and design low-energy, high-performance communication infrastructures for CMPs.

Analysis of network resources for several benchmarks shows that, utilization and hence energy consumption is application dependent and the desired performance can be achieved even without operating all resources at maximum specifications. To reduce the power consumption, we propose a leakage power-aware NoC architecture using power gated router based on the router utilization. To compute the utilization of routers, we propose an adaptive two-step estimation method that computes utilization at both global and local router levels. This hybrid estimation method provides an accurate prediction of router utilization with low run-time overheads. Using the utilization estimates, we reduce the switching and idle-state power consumption of WNoC architecture. To eliminate power-gating impacts and maintain the performance, we implement a deadlock-free Seamless Bypass Routing (SBR) strategy that bypasses a power-gated router.

Based on the utilization of routers, we propose a switching (dynamic) power-aware NoC architecture using Adaptive Multi-Voltage Scaling (AMS) mechanism to achieve significant energy saving. To implement the AMS based WNoC architectures, we also propose a multi-level voltage shifter along with efficient control mechanism that allows switching between two voltage levels from a given fixed set of voltage levels. But most wireless interconnects are implemented using a token passing protocol in which only a single paired is actively involved in data transmission at any given time. Hence, the wireless transceivers can be selectively switched on and off depending on the workload. This will improve the power efficiency of the network without affecting the overall network performance, especially when all the wireless transceivers are designed to operate at the same frequency and only one pair can use the channel at a time.

Since all these wireless links are not required all time, power-gated wireless transceivers can provide an effective solution for power efficient WNoC design. In this dissertation, to increase the power efficiency, we also propose the partially power gated transceiver for wireless interfaces (WIs) using AMS to reduce the idle-state power consumption based on the utilization of WIs. For packets transmitted over wireless links, receiver-end control strategy is proposed with WNoC. This enables effective power gating strategy for WIs as it eliminates periodic waking up of complete receiver chain. The proposed technique also reduces routing overhead and need of control signals significantly.

However, most existing WNoC architectures generally use omnidirectional antenna along with token passing protocol to access wireless medium. That limits the achievable performance benefits since only one wireless pair can communicate at a time. It is also not practical in the immediate future to arbitrarily scale up the number of non-overlapping channels by designing mm-wave transceivers operating in disjoint frequency bands. Consequently, we explore the use of directional antennas where multiple simultaneous wireless interconnect pairs can communicate. Concurrent wireless communications can result in interference. This can be minimized by optimal placement of wireless nodes. To address this, we propose an interference-aware Directional Wireless NoC (DWNoC) topology with optimal placement of WIs by incorporating planner log-periodic antennas (PLPAs). This DWNoC architecture enables the directional point-to-point links between transceivers and hence multiple wireless links can operate at the same time without interference. It also increases the energy efficiency of DWNoC as well as utilization of WIs significantly as compared to existing NoC architectures.

In addition, we also address the on-chip communication bottlenecks between Last Level Caches (LLCs) and Memory Controllers (MCs) to access off-chip memory. Communication between LLCs and memory controllers faces significant challenge due to the placement of memory controllers, high network latency, and switching strategy. Especially, as system size increases, the latency between caches and limited number of memory controllers increases, thereby degrading the memory performance. To overcome this, we propose an adaptive hybrid switching strategy with dual crossbar router to provide low latency paths between caches and memory controllers. The performance is further improved by finding the optimal number and placement of memory controllers with low overheads. To reduce the energy overhead of dual crossbar routers, we introduce partially drowsy and power gated techniques with routers in the proposed architecture.