Asynchronous 1R-1W dual-port SRAM by using single-port SRAM

Abstract

With the advancement in technology nodes, the number of components operating in different clock domains on System on Chip (SoC) increases. To support the processing of data between these components, the demand of an asynchronous multi-port memory on SoC is rising. This paper introduces an asynchronous multi-port memory with dedicated write and read ports. The memory architecture is based on the Single-Port SRAM (SP-SRAM) that can be generated in larger capacities with good performance compared to the Dual-Port SRAM (DP-SRAM). The proposed design has been evaluated by comparing existing dual-port 1R-1W and 2RW designs in Ultra Thin Body and Box Fully Depleted Silicon on Insulator (UTBB- FDSOI) technology. A 2048 words of 64 bit memory shows 15%, 35%, 28% and 4.5% improvement in read power, write power, read-write power and performance respectively over conventional 1R-1W DP-SRAM with equal area. The same size memory with area optimization technique shows 50% area advantage over conventional 1R-1W DP-SRAM but with degradation in performance.