High resolution low power discrete-time sigma-delta ADC with input offset compensation technique

Abstract

Audio applications necessitate precise data conversion from analog to digital domain. This high resolution conversion can be achieved by using Sigma-Delta architecture, which operates at oversampling rate and exhibits noise-shaping characteristics. The intent of this thesis involves design of discrete-time and continuous-time Sigma-Delta modulator using Input Common Mode Compensation Circuit. The proposed topology is 2nd order Sigma-Delta modulator, which employs a Cascade of Integrators in Feed-forward manner (CIFF). The initial stage of this work involves behavioral modeling of Sigma-Delta modulator, which is performed using Verilog AMS followed by circuit level implementation of the architecture using CMOS 28nm technology. The important aspect of the design involves compensation of input common mode variation on the performance of the operational amplifier and improving the resolution of the converter in discrete time ADC. The performance measurements achieved using proposed discrete-time modulator are SNR 97dB over signal bandwidth 28:8KHz and power dissipation of 0:3mW and performance measurements achieved using proposed continuous-time modulator are SNR 92dB over signal bandwidth 28:8KHz and power dissipation of 270_W