SRAM memory architecture

Abstract

Static Random Access Memory (SRAM) along with CMOS technology is scaling in different processors and system-on-chip (SoC) products rapidly and this has given us the need of innovation in the area of SRAM design. As, designing a larger SRAM cell would help us to reduce variations and increase the stability. Multiple assist schemes and design strategies has been used to increase the stability of memory cell as the role of these Assist schemes is to help in achieving a robust read or write operation This report presents the complete design of the SRAM sub-system architecture. The functioning of all the blocks of the architecture is explained in detail. Then the simulation of the complete architecture is given with the sizing of transistors and setting the initial conditions on cadence.