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FPGA implementation of multi-standard wireless transceiver via dynamic partial reconfiguration

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dc.contributor.author Deep, Gyan
dc.contributor.author Darak, Sumit Jagdish (Adviosr)
dc.date.accessioned 2018-01-30T05:28:52Z
dc.date.available 2018-01-30T05:28:52Z
dc.date.issued 2017-12-15
dc.identifier.uri http://repository.iiitd.edu.in/xmlui/handle/123456789/601
dc.description.abstract To support wide variety of services ranging from voice, high-speed data and multimedia, multi-standard wireless communication transceivers (MWCT) are desired. Such transceivers have the capability to adapt to any desired data rate, bandwidth and center frequency depending on the environmental conditions (for example, wireless channel, distance between transmitter and receiver, multipath fading, jammers etc.). Conventional MWCT employs Velcro approach where multiple communication standards are supported using parallel signal processing chains, one for each standard. This technique is straightforward and fast but there are also some major drawbacks associated with it like more area requirement and overall high power consumption and hence, not suitable for battery operated resource-constrained wireless transceivers. Due to the re-configurable architecture of Field Programmable Gate Array (FPGA), it has become an attractive platform to implement the wireless testbeds. Also, due to its inherent parallel architecture support, FPGA is ideal for implementing parallel operations like FFT/IFFT computation and digital filter implementation as required in these wireless transceivers. Excess area and power utilization of Velcro method can be reduced by using the dynamic partial reconfiguration technique. In this approach, only the blocks like qpsk modulation/demodulation blocks which need to be changed are swapped with the required blocks like 16-qam modulation/demodulation blocks according to the requirements. This approach leads to reduction of area utilization from sum of all the area required for implementing different versions of a particular block (i.e. parallel implementation) to area which is required by biggest version (in terms of area) of a particular block. Also, in this approach, the rest of design can work uninterruptedly while the reconfiguration is taking place. The main aim of this thesis is to demonstrate a working hardware testbed which implements a transceiver supporting dynamic partial recon_guration technique. The proposed MWCT can adapt the modulation scheme as well as the transmission bandwidth by partial reconfiguration of modulation and IFFT/FFT blocks of the transceiver. We discuss software controlled as well as hardware controlled approaches by which the partial reconfiguration can be enabled. We demonstrate the proposed approach on the 802.11a transceiver protocol realized on Zynq SoC using verilog. At the end, we compare the gain in area and power consumption over conventional Velcro approaches. Also, filters are implemented at the end of transmitter and beginning of receiver to demonstrate the implementation of filtered OFDM en_US
dc.language.iso en_US en_US
dc.subject Partial Reconfiguration en_US
dc.subject FPGA en_US
dc.subject Transmitter and Receiver en_US
dc.title FPGA implementation of multi-standard wireless transceiver via dynamic partial reconfiguration en_US
dc.type Thesis en_US


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