Abstract:
In advance technology nodes, static power consumption is a major component of total
system power in systems that do not continuously operate at very high clock frequency.
SRAMs not only contribute a major portion of SoC area but also of static power consumption.In this work, we propose an error amplifier based design to reduce retention leakage of a 4MB SRAM array. In 40nm LSTP technology, the amplifier consumes 81Nw power. The overall memory subsystem leakage power reduces by 50% from no retention case and 33% from the conventional retention solution at TT (25.) and by 75% from no retention & 69% from conventional solution at FNSP (140.). Monte Carlo analysis shows the 3_ variations are within guard band limits.
