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High voltage tolerant ESD protection circuit for plug and play devices

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dc.contributor.author Kulshreshtha, Mranal
dc.contributor.author Bahubalindruni, Pydi Ganga Mamba (Advisor)
dc.contributor.author Mathur, Shiv (Advisor)
dc.date.accessioned 2018-09-19T15:15:58Z
dc.date.available 2018-09-19T15:15:58Z
dc.date.issued 2018-05
dc.identifier.uri http://repository.iiitd.edu.in/xmlui/handle/123456789/639
dc.description.abstract ESD (Electrostatic Discharge) protection circuits are widely used in the semiconductor industry generally as on-chip solution to protect main circuit or Design Under Test (DUT) against electrostatic discharge. This electrostatic charge can be accumulated due to number of reasons such as mis-handing of machinery equipment, charge transfer from human body etc. If this charge is not bypassed, then it might result in the permanent failure of core integrated circuits or DUTs. Therefore, some effcient circuit design must be placed to discharge this high ESD stress. Typically, Electrostatic charge is in the range of kV, hence large sized devices are needed to discharge this high voltage. In addition to this, bias voltage stress above 1.8 V may lead to device breakdown in lower technology nodes such as 16 nm FINFET technology in spite of its unique advantage of allowing high speed operation with low power consumption. The major design challenges in designing ESD protection circuits are clamp area, which is the major area hungry block, high inrush current due to large sized devices, hot insertion problem and false triggering issues.In the state of art, existing ESD protection circuit are not able to survive for high voltage in sub-micron technology as it may lead to oxide breakdown due to low thickness. Further, these circuits are more sensitive to the hot insertion. In order to mitigate these design challenges, high voltage tolerant cascoded ESD protection circuit is proposed with a supply voltage of 3.3 V using 16 nm FINFET technology for devices such as ash drives, mobile devices etc. This circuit is designed keeping all constraints in mind such that the voltage stress across any device should not go beyond 1.8 V, which is breakdown voltage for the device. This ESD protection circuit can support 4 kV HBM and least inrush current in normal power on condition for speci_cation of 10 mA per instance. This proposed design has reduced the clamp area around 38 % and static current approximately 4 times as compared to the baseline circuit. This design supports plug and play feature, which generally su_ers from hot insertion problem. Simulation results shows that the proposed design is robust against PVT variations en_US
dc.language.iso en_US en_US
dc.publisher IIIT-Delhi en_US
dc.title High voltage tolerant ESD protection circuit for plug and play devices en_US
dc.type Thesis en_US

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