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Sub-1V CMOS bandgap reference for ultra-low power applications

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dc.contributor.author DALAL, NEHA
dc.contributor.author Hashmi, Mohammad S. (Advisor)
dc.contributor.author Rana, Vikas (Advisor)
dc.date.accessioned 2018-09-20T06:13:00Z
dc.date.available 2018-09-20T06:13:00Z
dc.date.issued 2018-07-13
dc.identifier.uri http://repository.iiitd.edu.in/xmlui/handle/123456789/640
dc.description.abstract BCD silicon process technology is invented by ST which plays a pivotal role in today’s industry. BCD is outcome of merging three different process technologies. The Digital, Analog and Power/High voltage elements are brought up on one single platform. This offers a unique range of voltage to cater large field of applications. Integration of best in class CMOS and HV devices is done which offers great link between design, technology and application. Bandgap reference voltage generator is one of the critical blocks of the analog counterpart of a macro which is responsible for generating a PVT compensated voltage. The desensitized voltage is further used as the reference for many other blocks such is level shifters, voltage regulators. As we are scaling down the technology the supply voltage is also scaled down. So the conventional BGR are no longer applicable to meet the needs. Thus the bandgap reference in subthreshold region are utilized to meet the desired range of voltage of operation. In this thesis, Bandgap Reference in subthreshold regime is designed using BCD9s (110nm) process technology. This is implemented to have applications in PCM/Flash memories designed in BCD technology at low supply voltages and in smart power applications. Two architecture are proposed: The voltage mode BGR with the supply voltage of 950mV. It provides the reference voltage of 700mV, with a maximum coefficient of variation of 5% and temperature coefficient of 50ppm/oC. The current mode bandgap reference is designed with a supply voltage of 650mV, which generates a reference voltage of 250mV with a very low temperature variation of 35ppm/oC. The static power consumption is 364nW at architecture level which is comparatively low which satisfies the ultra-low power applications. en_US
dc.language.iso en_US en_US
dc.publisher IIIT-Delhi en_US
dc.title Sub-1V CMOS bandgap reference for ultra-low power applications en_US
dc.type Thesis en_US

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