A successive approximation register based digital delay locked loop for clock and data recovery circuits

Abstract

The delay locked loop (DLL) is widely used in the electronics industry for implementing clock and data recovery circuits (CDR) in high-speed IOs. DLL contains first order closed-loop architecture, aligns the output clock to the reference clock, and reduces skew between two clocks across variations in process, voltage and temperature (PVT) by the help of the delay line. This circuit is always stable as it is a single pole system. DLLs can be broadly classified into two categories: analog DLL and digital DLL. The analog DLL has an analog controlling input to control the delay offered by the delay lines to reduce the skew between the input and the output clock of the DLL system. Digital DLLs on the other hand, have quantized steps for delay change in the delay line. This delay line is controlled by a digital code obtained from the controller. The Digital DLLs can easily adopt to technology changes as they do not have strict voltage headroom requirements like analog DLLs. Also, mostly standard cells are used to design Digital DLL which makes them portable. These characteristics make Digital DLLs an attractive choice for implementing clock and data recovery circuits for very advanced technologies.Lock time is one of the important parameter while designing DLL. It is decided by the type of controlling mechanism used in implementing DLL. In order to reduce the lock time, in this thesis work, the controller is implemented by Successive Approximation Register which reduces the lock time for proposed DLL by using binary search algorithm. To track the PVT variations, the SAR used has been modi_ed in such a manner that it uses binary search algorithm for locking the DLL and then turns into a counter, to track the PVT variations after locking. This DLL is designed in TSMC16nm FinFET technology. This technology has its own limitations with respect to the delay offered by the inverters and the amount of current an inverter can support. In order to mitigate the current consumption and hence power consumption, a timing controller has been proposed which helps the delay line achieving a resolution as small as 5ps for a frequency of 400 MHz whereas the state-of-art study shows that for lower frequencies, a delay resolution of at least 10ps has been reported. This circuit has a power consumption of only 240_W across corners whereas the state-of-the work has reported a power consumption in order of mW. The phase accuracy of the designed Digital DLL is 99.5% across corners in locked condition.