Investigation of timing of logic gates realized using probabilistic spin logic (PSL)

Abstract

Probabilistic Spin Logic (PSL) is a fascinating computing model composed of fundamental stochastic units called probabilistic bits (p-bits). A p-bit can be realized using low-barrier nanomagnets. It can be combined to implement Boolean functions with accuracy comparable to that of a traditional digital logic circuit. Moreover, a PSL circuit can also be used to compute the inverse of a Boolean function, a trait that is missing from conventional digital circuits. In this research, the application of PSL to realize complex Boolean functions has been examined using simulations. Further, an investigation into the timing of complex logic gates implemented using PSL has been carried out. A methodology to characterize delay as an intrinsic property of the logic gates independent of the way the delay is computed is proposed. The correctness of the proposed methodology using a few Boolean functions has been demonstrated in this work. Additionally, the factors that govern the delay of PSL circuits are examined and a technique to reduce the delay has been proposed.