Abstract:
Technology scaling and continuous increase in data rate have been the driving forces
leading the innovations in high-speed interfaces. With the growing need for ultra-low
power and high-speed data rate signaling, integrated systems-on-chip have become mainstream critical components in the modern computing system. Traditional parallel links have been used in circuits for a long time, where the skew between clocks and data lanes in the link becomes difficult to control with the faster data rate. The alternate solution is to go with faster serial links (reduced pin count and area). Traditional parallel links like PCI got replaced by high-speed serial IO standards like PCI-e, SATA, USB, TBT, DP, HDMI, M-PHY which serve multiple applications like the processor to processor or processor to peripheral communication. Serializer and Deserializer are the main blocks of High-Speed IO links. Serializer at the transmitter side converts the parallel data stream into a serial data stream while Deserializer at the receiver side converts back serial data stream into a parallel data stream. This allows for higher data rate, less number of interconnect pins, area, and cross-talk compare to parallel data transmission.
This work presents the design and implementation of 28Gbps Serializer and Deserializer for High-speed IO links. An overview of high-speed IO links with a brief discerption of all the blocks of the system is presented. The fundamentals to design high speed and low power Serializer and Deserializer have been discussed along with the different architecture of Flip-flop, Serializer, and Deserializer. The proposed circuit is implemented in TSMC 16 nm CMOS technology. Simulation outcome has shown that Serializer and Deserializer can support 28Gbps data rate with maximum power consumption 8.22mW (Serializer) and 3.20MW (Deserializer) with a power efficiency of 0.29pJ/bit (Serializer) and 0.12pJ/bit (Deserializer), making the secircuits quite useful for High-Speed IO links. Simulation results show that the proposed design is robust against PVT variation.
