Abstract:
A high resolution 77GHz linear chirp signal synthesizer for a monostatic frequency modulated continuous wave (FMCW) radar is presented. The proposed linear frequency modulation design uses a fixed frequency multi-stage phase-locked loop (N-PLL) for generating a 77GHz chirp signal. The novel design feature is the incorporation of an additional digital control block clocked from a derived signal output from the N-PLL. A reference oscillator activates the chirp generator block. The clock provided to this block is from the intermediate stage of the N-PLL. Therefore, the generator is clocked at Gigahertz rather than a few Megahertz. This clocking signal can be seen as the sampling frequency of the chirp signal generated. The frequency resolution of the generated chirp signal increases, keeping the bandwidth of chirp intact. The digital block is based on lookup tables. Individual lookup tables and circuits are used when the clock provided by the PLL is of constant frequency, and when the clock provided is "chirpy" due to PLL itself being chirpy. Simulation results using an ideal PLL demonstrate the workability of
the proposed method. The all-digital open-loop architecture is simulated with the PLL to generate a high resolution, low noise narrowband chirp with an SFDR performance above
100dB at the PLL output. The digital design does not constrain the fixed frequency PLL design in any way. The resulting chirp signal conformed to above 99.95% linearity. The phase noise modeling of first-order has also been done in the Voltage Controlled Oscillator block of PLL, and relative deviation results of simulation with Gaussian random input have been considered. The approach provides excellent frequency resolution, thereby increasing the unambiguous range of the radar. The high bandwidth of chirp ensures an excellent radar range resolution while the moderate duration of chirp provides a right balance between velocity resolution and maximum unambiguous velocity. Also, the statistics pertaining to these two are improved as a whole. The
distortion seen at output manifests only due to PLL non-idealities, of which analysis has been performed, and results have been discussed. The distortion seen at output manifests only due to PLL non-idealities, of which analysis has been completed, and results have been presented. The model can be used alongside applications that require high frequency resolution chirps with large bandwidth
