Abstract:
One of the most widely used blocks in Communication System design is Phase locked loop (PLL). PLLs are used as clock generators, frequency synthesizers, clock recovery in microprocessors and many other applications. The key block in design of PLL is the Voltage Controlled Oscillator (VCO). Latest gadgets like smart phones, smart watches, televisions, car electronics are synced to a clock generated by VCO.
This thesis focuses on design of LC voltage-controlled oscillators on 40nm technology. With the technology being scaled down, the supply voltage is also scaled down to prevent device breakdown. This results in reduced output swing and degraded phase noise. The quality factor of the LC resonator is low at higher frequency which makes it very difficult to design a low voltage VCO. The main challenges are phase noise, area, performance and variations.
This thesis presents the design of low power, low phase noise LC VCO at 800MHz output frequency. The design is implemented on 40nm technology at 1.31V supply voltage achieving a phase noise of -131.7dBc/Hz. The power consumption is 4.3mW. The PVT variations of the design are 4% of nominal value for frequency and 6.8% of nominal value for phase noise. Monte Carlo analysis is also carried out and results are reported.
