Nanoscale tunnel field-effect transistors for digital circuit applications: design and analysis

Abstract

Metal–oxide–semiconductor field-effect transistor (MOSFET) has been used for decades in the semiconductor industry. However, with the continuous downscaling of the device dimensions to the nanometer regime, conventional MOSFETs have reached a fundamental physical limit that restricts the subthreshold swing of the device to ≥ 60 mV/dec, at room temperature. It prohibits scaling threshold voltage below a specific limit; otherwise, the OFF-state current in the device becomes too high. Therefore, at nanoscale dimensions, conventional MOSFET suffers from high leakage current, non-scalability of the supply voltage, and high power consumption. In recent times, tunnel field-effect transistors (TFETs) have attracted a great deal of attention as an alternative to MOSFETs at nanoscale device dimensions. A TFET is structurally similar to a MOSFET except that in a TFET, the drain and source are oppositely doped in contrast to a MOSFET where the drain and the source are doped similarly. Moreover, the switching mechanism of a TFET is based on band-to-band tunneling, which allows TFET to exhibit subthreshold swing below 60 mV/dec, at room temperature. It makes TFET suitable for low-voltage and energy-efficient digital circuit applications. However, there are some challenges in the application of a TFET in digital circuits. These challenges arise primarily due to the low ON-state current and high ambipolar current. Further, scalability is another challenge for tunneling devices at nanoscale dimensions. TFETs are known to exhibit degraded electrical characteristics at small gate lengths, primarily due to direct source–to–drain band-to-band tunneling. Moreover, various studies have shown that TFETs are highly susceptible to process-induced variations such as random dopant fluctuations, non-abrupt source–channel junction, the shift in gate-edge with respect to source, and variation in work-function. These variations can lead to degraded electrical characteristics of the device at the nanoscale. This work aims to tackle the above-mentioned problems in a TFET. In this work, a technique of suppressing ambipolar current has been proposed by inserting a drain-pocket (DP) at the drain–channel interface in a double-gate TFET (DGTFET). The DP reduces BTBT on the drain-side by increasing the tunneling barrier width and decreasing the band overlap. It results in a reduction of ambipolar current from 5 × 10−6A/μm in the DGTFET to 1 × 10−14A/μm in the DP-DGTFET for complete range of negative gate voltage (−VDD ≤ VGS ≤ Gnd) and high drain doping, such as 1 × 1020 atoms/cm3. To tackle the problem of scalability of TFETs, a silicon–on–insulator TFET (SOI-TFET) has been proposed. A ground plane (GP) is incorporated inside the buried-oxide (BOX) in the SOI-TFET. It is demonstrated that the addition of GP leads to increased effective drain–to–source distance, which suppresses the direct source–to–drain tunneling. Therefore, the OFF-state current (IOFF) is suppressed even at short gate lengths, and the device becomes more scalable. Further, the ambipolar current (IAMB) is suppressed even at short gate lengths. A novel TFET demonstrating within-channel tunneling has been proposed using a dual-material gate (DMG) architecture. The gate material work-functions are chosen such that a sharp transition in the energy bands is obtained at the junction of high–low work-function materials. Therefore, tunneling occurs at the DMG interface (referred to as within-channel tunneling) rather than at the source–channel junction. The sharp transition at the DMG interface leads to an inherent lateral electric field and a strong gate control over the BTBT region. Therefore, several electrical parameters such as subthreshold swing, ON-state current, etc., improve in the proposed TFET. It becomes immune to variations in source doping concentration and gate-edge shift at the source–channel interface. However, the impact of work-function variations and interface trap charges in the proposed device is important and needs to be tackled. Additionally, this work explores implementations that can exploit the unique characteristics of TFETs to realize logic functions. Separate single tunneling devices realizing logic functions such as OR, NAND, NOR, AND, XNOR and XOR have been proposed. Further, these devices can be combined in a complementary manner to obtain different logic gates. These gates are compact since fewer transistors are required compared to conventional complementary– metal–oxide–semiconductor (CMOS) logic gates. For instance, realizing AND gate using CMOS requires six transistors, whereas using the proposed devices, the AND gate can be realized using only two transistors. In summary, this work contributes towards making TFETs more suitable for digital circuit applications. This has been achieved by proposing different TFET structures that ameliorate one or more problems in the conventional TFET. Moreover, the unique properties of TFETs, such as ambipolar conduction, the impact of the gate–source overlap, symmetric operation, and modulation of current within the channel, are utilized to realize all two-input logic functions using a single tunneling device