http://repository.iiitd.edu.in/xmlui/handle/123456789/627 2026-04-11T03:17:55Z 2026-04-11T03:17:55Z K, Tejaswini Bahubalindruni, Pydi Ganga Mamba (Advisor) Mathur, Shiv Harit (Advisor) http://repository.iiitd.edu.in/xmlui/handle/123456789/644 2018-09-25T13:19:32Z 2018-05-01T00:00:00Z

Continuous time linear equalization based gigabit receiver for parallel interface K, Tejaswini; Bahubalindruni, Pydi Ganga Mamba (Advisor); Mathur, Shiv Harit (Advisor) Modern processors are capable of working at a very high frequency with the advent of technology scaling. However, memory limits the overall speed of operation. In order to take complete advantage of these modern high-performance processors, it is essential to improve the data transfer rates in the memory. As per open NAND ash interface (ONFI) standard, the current data rate is around 800MBps. Between every successive ONFI standard, a 100% improvement in data rate has been observed. By extrapolating the existing trend, the data rate of next generation of ONFI can be about 1600MBps. This project aims at achieving 1333MBps to support an industrial need. Since the speed focused on Silicon is 1333MBps, the thesis strives to achieve 1400MBps in order to accommodate parasitics. At this high frequency, the channel response deteriorates because of dielectric loss and Inter-Symbol Interference (ISI). Additionally, crosstalk in parallel interface degrades the signal integrity. The technique used to restore the channel loss is called equalization. The thesis presents a design of Continuous Time Linear Equalization (CTLE) based gigabit receiver for ONFI parallel interface on 16nm FinFET technology. The design consists of a CTLE, a latch, a Current Mode Logic (CML) to Complementary MOSFET (CMOS) converter and a duty cycle corrector (DCC). A novel design has been proposed to support rail to rail Input Common Mode Range (ICMR) of the receiver to provide exibility to the transmitter. This receiver compensates an estimated channel loss of 4dB at 1400MHz and provides a dc-gain of 10dB. Further, it maintains 50_1:5% duty cycle to support Double-Data-Rate(DDR) (2.8GbBs). For a given ICMR,a power efficiency of 1.4pJ/bit is achieved which is superior to the state-of-art designs. However, in order to support complete rail to rail ICMR the novel design was showing 4.7pJ/bit.

2018-05-01T00:00:00Z Banerjee, Saptak Saurabh, Sneh (Advisor) http://repository.iiitd.edu.in/xmlui/handle/123456789/642 2018-09-25T13:24:21Z 2018-07-01T00:00:00Z

Realizing and functionality using single tunnel field-effect transistor Banerjee, Saptak; Saurabh, Sneh (Advisor) In this thesis, a single Double-Gate Tunnel Field-Effect Transistor (DGTFET) is proposed to realize the AND functionality. Using two-dimensional device simulations, it is shown that a single DGTFET can realize logic functionality by biasing the two gate terminals independently. The key elements in obtaining the required functionality using a DGTFETare:1. Employing a gate-source overlap2. choosing an appropriate silicon body thickness.The two-dimensional device simulations demonstrate that the electrical characteristics of the proposed device correctly implements the AND functionality. Specifically, the drain current under the biasing conditions at two inputs 11, 01, 10 and 00 are in the order of 1 _ 10􀀀8, 1 _ 10􀀀15 1 _ 10􀀀15 and 1 _ 10􀀀15 respectively. Therefore, an impressive ION=IOFF ratio of 1 _ 108 is attained.Further, it is demonstrated that realized device is operational even for low supply voltages.But the ION=IOFF ratio keeps on deteriorating as the supply voltage is reduced.However, for future applications, it must be ensured that the proposed device must exhibit sufficiently high ION=IOFF ratio, especially at low supply voltages. In this thesis, the challenges involved in enhancing the ION=IOFF ratio in a TFET that realizes the AND functionality, are investigated. The study shows that the techniques that boost the ION in a TFET, for example using a low bandgap material, does not necessarily enhance the ION=IOFF ratio in the device. This is primarily due to challenges involved in turning-OFF the device when only one of the terminals is biased at logic “1”. Further, the efficacy of using Dual Material Gate (DMG) and optimizing silicon body thickness to improve the ION=IOFF ratio is explored.

2018-07-01T00:00:00Z Mittal, Priyanka Bahubalindruni, Pydi Ganga Mamba (Advisor) Odedara, Bhavin (Advisor) http://repository.iiitd.edu.in/xmlui/handle/123456789/641 2021-12-15T05:19:31Z 2018-07-01T00:00:00Z

A successive approximation register based digital delay locked loop for clock and data recovery circuits Mittal, Priyanka; Bahubalindruni, Pydi Ganga Mamba (Advisor); Odedara, Bhavin (Advisor) The delay locked loop (DLL) is widely used in the electronics industry for implementing clock and data recovery circuits (CDR) in high-speed IOs. DLL contains first order closed-loop architecture, aligns the output clock to the reference clock, and reduces skew between two clocks across variations in process, voltage and temperature (PVT) by the help of the delay line. This circuit is always stable as it is a single pole system. DLLs can be broadly classified into two categories: analog DLL and digital DLL. The analog DLL has an analog controlling input to control the delay offered by the delay lines to reduce the skew between the input and the output clock of the DLL system. Digital DLLs on the other hand, have quantized steps for delay change in the delay line. This delay line is controlled by a digital code obtained from the controller. The Digital DLLs can easily adopt to technology changes as they do not have strict voltage headroom requirements like analog DLLs. Also, mostly standard cells are used to design Digital DLL which makes them portable. These characteristics make Digital DLLs an attractive choice for implementing clock and data recovery circuits for very advanced technologies.Lock time is one of the important parameter while designing DLL. It is decided by the type of controlling mechanism used in implementing DLL. In order to reduce the lock time, in this thesis work, the controller is implemented by Successive Approximation Register which reduces the lock time for proposed DLL by using binary search algorithm. To track the PVT variations, the SAR used has been modi_ed in such a manner that it uses binary search algorithm for locking the DLL and then turns into a counter, to track the PVT variations after locking. This DLL is designed in TSMC16nm FinFET technology. This technology has its own limitations with respect to the delay offered by the inverters and the amount of current an inverter can support. In order to mitigate the current consumption and hence power consumption, a timing controller has been proposed which helps the delay line achieving a resolution as small as 5ps for a frequency of 400 MHz whereas the state-of-art study shows that for lower frequencies, a delay resolution of at least 10ps has been reported. This circuit has a power consumption of only 240_W across corners whereas the state-of-the work has reported a power consumption in order of mW. The phase accuracy of the designed Digital DLL is 99.5% across corners in locked condition.

2018-07-01T00:00:00Z DALAL, NEHA Hashmi, Mohammad S. (Advisor) Rana, Vikas (Advisor) http://repository.iiitd.edu.in/xmlui/handle/123456789/640 2020-01-28T04:35:16Z 2018-07-13T00:00:00Z

Sub-1V CMOS bandgap reference for ultra-low power applications DALAL, NEHA; Hashmi, Mohammad S. (Advisor); Rana, Vikas (Advisor) BCD silicon process technology is invented by ST which plays a pivotal role in today’s industry. BCD is outcome of merging three different process technologies. The Digital, Analog and Power/High voltage elements are brought up on one single platform. This offers a unique range of voltage to cater large field of applications. Integration of best in class CMOS and HV devices is done which offers great link between design, technology and application. Bandgap reference voltage generator is one of the critical blocks of the analog counterpart of a macro which is responsible for generating a PVT compensated voltage. The desensitized voltage is further used as the reference for many other blocks such is level shifters, voltage regulators. As we are scaling down the technology the supply voltage is also scaled down. So the conventional BGR are no longer applicable to meet the needs. Thus the bandgap reference in subthreshold region are utilized to meet the desired range of voltage of operation. In this thesis, Bandgap Reference in subthreshold regime is designed using BCD9s (110nm) process technology. This is implemented to have applications in PCM/Flash memories designed in BCD technology at low supply voltages and in smart power applications. Two architecture are proposed: The voltage mode BGR with the supply voltage of 950mV. It provides the reference voltage of 700mV, with a maximum coefficient of variation of 5% and temperature coefficient of 50ppm/oC. The current mode bandgap reference is designed with a supply voltage of 650mV, which generates a reference voltage of 250mV with a very low temperature variation of 35ppm/oC. The static power consumption is 364nW at architecture level which is comparatively low which satisfies the ultra-low power applications.

2018-07-13T00:00:00Z