http://repository.iiitd.edu.in/xmlui/handle/123456789/956 2026-04-10T22:13:09Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1707 Implementation of an accelerator for edge computing devices Gupta, Garvit; Deb, Sujay (Advisor) Edge computing is a distributed computing paradigm that brings computation and data storage closer to the location where it is needed to improve response times and save bandwidth. Two important aspects of edge computing are low cost and low power. Now a days, because of edge computing many edge devices are being fitted with deep CNN based accelerators which are able to do object identification and detection on the fly. Our main focus will be primarily on CCTV or Closed circuit television cameras which are one such edge-devices that are being widely used for video surveillance techniques across the world. By placing CCTV cameras at strategic locations, we can help prevent acts of vandalism, break-ins, and other serious crimes. This has led to its widespread use across the globe and therefore it is equally important that CCTV just not remain a device for capturing and transmitting the data to cloud centres but also should be functionally efficient in processing and giving meaningful outputs of the data in real-time. To make CCTV cameras an active device, it is imperative to put some processing element. With this in mind, in the first semester, we first designed a low cost RISC V based processor with only a limited set of instructions so that it incurs less power. But for this, new custom compiler along with different set of software ecosystem has to be generated which altogether poses a problem of different domain. Moreover, open source hardware community would not be able to take full advantage of it. To remove this problem, we moved to an accelerator based approach. We first designed the accelerator for primitive image processing applications viz. blurring and edge detection so as to get acquainted with challenges and intricacies involved while designing an accelerator. In the current semester we extended the accelerator to deep CNN accelerator where we studied and analyzed the quantization techniques to improve the hardware utilization for edge devices and scratchpad based memory system for improving the communication bottleneck between host CPU and accelerator specifically designed for deep learning applications. 2021-05-10T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1133 A web app for all the cultural fests and events at IIITD Chauhan, Nikhil; Shah, Rajiv Ratn (Advisor); Kumaraguru, Ponnurangam (Advisor); Singh, Sehaj FEST@IIITD is a part of the Umbrella OSA (Online Student A airs) app and serves the purpose of bringing together and managing all the cultural events happening at our campus. It provides the overview for the events, along with the capability to add personalised announcements and events on the calendar. It will allow the organising teams to communicate with their volunteers easily and without any hassle. It will prove to be useful to the Organising Committee to give a seamless and enriched experience of the fests at IIITD. 2021-01-01T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1117 Reconfigurable and intelligent architectures for deep learning algorithms Rajesh, Rohith; Darak, Sumit Jagdish (Advisor); Jain, Akshay (Advisor) Throughout the course of this BTP, we e ciently implement a Deep Learning Architecture(DLWSS) for Spectrum Sensing problem on the FPGA. This involved training the model from scratch on Pytorch/Keras, extracting the weights and designing the preprocesssing and the DL model from scratch on FPGA. The developed model is benchmarked with existing iterative algorithm(OMP) for di erent types of sparsity and channels. DLWSS is optimised using Hardware Software Co- Design(HSCD) and word length optimization principles in terms of Power, Performance and Area. Finally, a basic UI is developed to visualize predictions of the model on Hardware in real time. Semester 1 was used to acquire required skillset and train the DLWSS model on a software Framework and get a basic version of Hardware implementation done. Semester 2 was used to develop the optimized implementation of DLWSS on HW along with Preprocessing Model on SW to get end to end system on the FPGA along with exploring Quantization and HSCD . Chapter 13 shows the progress made in the current semester of the BTP. The report is in continuation to the report submitted for the previous 2 semesters of the BTP. 2021-12-01T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1114 Multimodal fake news analysis and detection Dhawan, Mudit; Kumaraguru, Ponnurangam (Advisor); Shah, Rajiv Ratn (Advisor) Fake News has become the curse of our time. Online social media networks provide a low-cost platform to facilitate information and fact sharing, but it fails to o er any quality control. As the number of people receiving their daily news through these platforms increases, it becomes a signi cant problem for the government and other organizations. Fake News articles leverage the multimedia content posted on the platforms and mislead the reader through fabricated image(s) or text (title and text body) accompanying it. Many organizations have started an initiative to provide de-bunked fake news, i.e., fact-checked and veri ed counterfeit news items oated on various social media platforms by human fact-checkers. Though this human intervention is a good start towards eradicating this evil, it can not be feasible at a larger scale providing human fact-checked information for every post on social media. The scalability of this human fact-checked information isn't the only issue, but the promptness of such accurate information becomes crucial in this digital age. To address this problem, we aim to analyze multimodal fake content from platforms supporting online journalism (including various social media platforms) to extract meaningful features better and design an all-inclusive early-stage Automated Fake News Detection System. 2021-12-01T00:00:00Z