http://repository.iiitd.edu.in/xmlui/handle/123456789/1320 Year-2023 Sat, 11 Apr 2026 13:10:53 GMT 2026-04-11T13:10:53Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1739 B.Tech project on functionally redundant genome clusters Reddy, Vemula Thushar; Arvind; Ghosh, Tarini Shankar (Advisor) This project aims to develop computational pipelines to cluster microbiomes from different geographic locations and disease phenotype based on the similarity in their functional signatures. This initiative has built an extensive database of functional feature count matrices for 71,140 high-quality metagenomes from their annotation files. The database will give information about several functional features like the Carbohydrate active enzymes for different microbial species, Orthologous groups, KEGG reaction pathways, etc. Locality-sensitive hashing techniques have been deployed to find the cluster of functionally similar genomes/taxa as well as similar microbiomes based on the functional profiles. This framework will be implemented to develop better diagnostic methodologies for the human gut microbiome. Wed, 29 Nov 2023 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/1739 2023-11-29T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1734 IMC hardware accelerator evaluation framework Marwah, Sahas; Dubey, Suyash Kumar; Grover, Anuj (Advisor) Neural networks have emerged as a powerful tool in machine learning and deep learning, showcasing remarkable capabilities in image recognition, natural language processing, and autonomous decision-making tasks. However, the execution of neural network models often requires substantial computational resources, leading to prolonged execution times. This computational burden hinders real-time deployment in resource-constrained environments. To address this challenge, hardware accelerators have emerged as a promising solution. Hardware accelerators are specialized computing units designed to efficiently execute specific computational tasks, offering significant performance improvements over traditional software-based implementations. In this paper, we propose a comprehensive evaluation framework for hardware accelerators in implementing neural networks. The framework will consider various aspects of accelerator performance, including execution time and resource utilization, and take into account the impact of different neural network architectures and hardware platforms. By evaluating the execution time and accuracy of standard neural networks compared to those with hardware accelerators performing in-memory computation of multiple convolution operations, we demonstrate the effectiveness of implementing neural networks using hardware accelerators. This framework will provide researchers and developers with a systematic approach to selecting and designing specialized computing units for neural network applications, enabling informed decision-making and improving overall system efficiency. Fri, 01 Dec 2023 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/1734 2023-12-01T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1733 Implementation of cache-coherent NoC for multi-core systems Pai, Ullas Ravindra; Deb, Sujay (Advisor) In a multi-core system, each core has its own local cache, which stores copies of data from the main memory. In a single program, different threads might run on separate cores to perform parallel tasks. These threads could be working on different aspects of the same problem and likely share the same data. When multiple cores must work with the same data, coherency mechanisms ensure that all cores see a consistent view of that data. Directory-based coherence is commonly used in Network architectures to maintain data coherency between the cores. Directory protocols were originally developed to address the lack of scalability of snooping protocols. The aim is to establish the proof of concept of Cache coherence protocols - improving the execution time of programs in systems trying to exploit Multi-threaded workloads. We shall see how coherence requests, in theory, get translated during implementation, starting with an unsophisticated protocol. We shall go over the need for coherence, the thought processes behind the protocol, the design of various components and their implementation, and finally, the validation of the designs. Tue, 05 Dec 2023 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/1733 2023-12-05T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/1624 Design thinking for social innovation: the tale of humankind Gupta, Aniket; Grover, Anuj (Advisor); Sharma, Jyoti (Advisor) Wed, 29 Nov 2023 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/1624 2023-11-29T00:00:00Z