http://repository.iiitd.edu.in/xmlui/handle/123456789/143 Fri, 10 Apr 2026 20:02:31 GMT 2026-04-10T20:02:31Z http://repository.iiitd.edu.in/xmlui/handle/123456789/174 Improvement in static timing analysis for early ta-signoff closure in soc flow at very deep submicron nodes Singh, Vinod Kumar; Biswas, R. N. (Advisor) An approach is proposed to improve static timing analysis for early TA-signoff closure at Very Deep Sub-Micron (V-DSM) nodes. At higher technology nodes (>100nm) the timing path delay is governed mainly by the cells, and hence the traditional corners (PVT) are sufficient to decide proper timing and functionality of SoC. With technology scaling, the dimension of transistors and interconnects get reduced, resulting in decrease in the driving capability of cells and a simultaneous increase in the resistance of interconnects. This makes the contribution of interconnects to the path delay grow in comparison to the cell contribution. In addition, PVT variations increase with scaling, affecting the cells as well as interconnects. This results in drastic increase in timing analysis corners to achieve the desired functionality of system on chip (SoC). The growing demand of different functionalities in SoC has increased the number of modes and hence the number of analysis views (combination of modes and corners). That makes timing complex, which is further enhanced due to high frequency requirement. Timing complexity makes STA technique time-consuming. To reduce time, multiple corners run in parallel using Distributed Multi-Mode-Multi-Corners (DMMMC) technique rather than MMMC technique which is operated sequentially. As SoC size increases (size – number of instances), it becomes more and more difficult for MMMC technique to perform the job adequately. DMMMC saves time but not so significantly as number of modes also increases simultaneously. Large SoCs require each corner to be run in parallel on multiple machines, and hence cost per corner increases. To save host machine cost and machine run time, it is desired to reduce timing corners. This can be done by determining and exploiting the correlation between different parameters and their effects on timing. The proposed idea has been carried out by measuring slack variation across the available corners. Three critical corners, out of the 12 corners provided by foundry, have been determined with ± 2-5 % variation: one for hold check and two for setup check. Now STA is limited to only these critical corners before final TA-signoff. By utilising these critical corners the machine license requirement as well as the machine run time can be reduced to 25%. This results in increased productivity of the organization while maintaining quality as well, by decreasing TA- cycle for early TA-signoff. Sat, 06 Sep 2014 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/174 2014-09-06T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/173 Analysis and estimation of jitter sub-components Sharma, Vijender Kumar; Deb, Sujay (Advisor) Maintaining quality of signal transmission is a major challenge with the increasing speed of data transmission in Nano-scale VLSI technology. The decreasing voltage margins at the same time, makes it even stringent to maintain Power Integrity (PI) and Signal Integrity (SI) in high speed systems. Jitter is an important phenomenon of signal integrity. It is the difference of expected transition edges to their actual transition edges. As the data rate of serial data pattern gets higher, the bit interval time gets shorter accordingly and thus the set-up time and hold-time requirements have very less margins for designers. If the jitter exceeds beyond its specified budget, the set up time and hold time can be violated in the system. To mitigate or reduce these effects, the causes of jitter in the circuit need to be identified. That is why the decomposition of jitter into its component is useful. With the help of jitter components segregation the time required to test a link for its bit error rate can be reduced. Jitter can be classified into two major components called Deterministic Jitter (DJ) and Random Jitter (RJ). Deterministic jitter is bounded in nature while random jitter is unbounded. DJ has specific causes and is predictable while RJ is non-predictable and uncorrelated to data pattern. DJ is caused by crosstalk, Electromagnetic Interference (EMI), data pattern, etc. On the other hand, thermal noise, phase noise, process variations are the root causes of RJ. DJ can further be categorized into Periodic Jitter (PJ) and Data Dependent Jitter (DDJ). PJ is periodic, and bounded in nature. It is caused by PLL comparator, crosstalk, external noise coupling, etc., while DDJ depends on the both data being currently transmitted and the data that has been already transmitted. Inter-Symbol Interference (ISI) and Duty Cycle Distortion (DCD) are sub-components of DDJ. Reflection, discontinuities, limited bandwidth of the channel, threshold variations are the major root cause of DDJ. In this thesis, comparisons of different types of jitter estimation techniques, their strength and limitations are discussed. Further, mathematical models of different jitter sources are implemented. Finally, we introduced a new technique for ISI estimation from total jitter using clock pattern. The results of these algorithms are extensively validated with Agilent ADS. Sat, 06 Sep 2014 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/173 2014-09-06T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/172 Executable model based design methodology for fast prototyping of mobile network protocol : a case study on mipi lli Shah, Rahul Kumar; Fell, Alexander (Advisor) Future mobile communication systems incorporate more sophisticated functionalities which im- prove their performance and increase their complexity. In order to reduce their time to market, the RTL development as well the simulation time of the prototyping phase has to be improved. This work presents a solution for improving the prototyping time by using Model Based Design approach comprising of Simulink HDL coder, HDL Verifier and rapid FPGA prototyping by means of FPGA in loop co-simulation. As a case study, the MIPI Low Latency Interface (LLI) layer protocol is implemented. The results presented in this report demonstrate that hardware acceleration based on reduction in prototyping time can be achieved by reducing the RTL development time and simulation time needed to validate the behavior of the design under test and enabling FPGA in loop co- simulation. In this dissertation comparison of the automatic generated HDL code from the Simulink HDL coder to that of manual hand-written code is performed. The comparison targets the time to market, area, power and timing constrains for the Data Link Layer (DLL) of MIPI LLI for both the procedures. Moreover, this dissertation discusses the limitation associated with Simulink Model Based Design methodology with a test case, modeling of single cycle latency CRC algorithm. The automatic HDL code generated from the Simulink Model Based Design using MATLAB R2013a, and the manual hand-written Verilog code for the Data Link Layer are synthesized for CMOS 45 nm standard cell ASIC technology. The comparison result shows that time to market value is reduced by more than half with significant decrease of 11% to 17% in the operating speed, the area and power consumption also increases by 25% and 29% respectively. Keyword- Area, Data Link Layer, Executable Model Based Design, FPGA in loop, Low Latency Interface, power, Rapid prototyping, Simulink HDL coder, time to market, timing. Sat, 06 Sep 2014 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/172 2014-09-06T00:00:00Z http://repository.iiitd.edu.in/xmlui/handle/123456789/171 Study, analysis and modeling of electromigration in SRAMs Kumar, Neeraj; Hashmi, Mohammad S. (Advisor) Today, the VLSI industry is matching the pace with the Moore‟s law which states that in every 18 months the number of transistors on integrated chip would get doubled. This essentially means that with the advancement of technology the size of MOSFET decreases and this in turn leads to miniaturization of wires connecting these devices. However, current flowing through these connecting wires does not decrease in appropriate proportion with the advancement in technology and as a consequence there is steep rise in the current density across integrated circuit. The increased current density may eventually result in failure of chips over a period of time due to a phenomenon called Electromigration. SRAM memories are prone to Electromigration effect considering that there is rapid advancement in its design and fabrication technology. This has the detrimental effect on the reliability of these chips. It is therefore imperative that each SRAM chips are subjected to Electromigration test in order to determine their reliability over a period of time. This additional step introduces delays in the final taping out of the chip. Conventionally, as a standard the Electromigration test is carried out in three steps using four commercially available tools. First, the capacitance of all nets along with devices is extracted. Second step estimates current in the nets followed by the generation of equivalent resistance in the nets of SRAM chips. Last step involves generation of results that provides information about the current limit and the dependence of flowing current on the associated parameters. This method is accurate but is complex and takes humungous amount of time as well as has high operating cost due to use of four tools. In this thesis work, we have developed a novel methodology which is simpler and is much faster (more than 1000 times) than the conventional technique. In addition, the proposed technique has very less operating cost. In summary, this modeling methodology requires just the Electromigration data of three memory instances i.e. one memory instance having lowest no. of bits and lowest no. of rows, second memory instance having lowest no. of bits but highest no. of rows, and third memory instance having highest no. of bits but lowest no. of columns. With this much information, the technique allows determination of the Electromigration data of any memory instance. This new technique deduces results which match favorably with those obtained from standard methodology. Fri, 05 Sep 2014 00:00:00 GMT http://repository.iiitd.edu.in/xmlui/handle/123456789/171 2014-09-05T00:00:00Z