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Now showing items 1-10 of 15

A practical methodology to waive marginal timing violations using machine learning

Kumar, Rajat; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2022-07)
Implementation of neuromorphic computing framework using tunneling-based devices

Gupta, Abhinav; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2024-04)
Leveraging LLMs for automatic incremental design implementation

Shukla, Shivam; Choudhary, Utkarsh; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2025-07-22)
Realizing and functionality using single tunnel field-effect transistor

Banerjee, Saptak; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2018-07)
Improving the retention time of a dopingless 1T DRAM using gate engineering

Agarwal, Nimish; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2019-07)
Analysis of circuits with partially correlated multi-Vt cell variations using sensitivity modeling and propagation

Ubaida, Mohd Abu; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2025-05-19)
Investigation of timing of logic gates realized using probabilistic spin logic (PSL)

Bhatia, Ishan; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2019-07)
Static timing analysis using ML models

Kumar, Jatin; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2024-12-11)
An artificial neural network based incremental placer for wire length reduction

Gagandeep; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2022-08)
Investigation of multiple input switching impact at advanced node (7nm)

Chowdary, Nekkanti Vignesh; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2024-12-12)

Now showing items 1-10 of 15